MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
4-Bit Binary Counter
The MC10H016 is a high–speed synchronous, presettable, cascadable
4–bit binary counter. It is useful for a large number of conversion, counting and
digital integration applications.
•
Counting Frequency, 200 MHz Minimum
•
Improved Noise Margin 150 mV (Over Operating Voltage and
Temperature Range)
•
Voltage Compensated
•
MECL 10K–Compatible
•
Positive Edge Triggered
MAXIMUM RATINGS
Characteristic
Power Supply (VCC = 0)
Input Voltage (VCC = 0)
Output Current — Continuous
— Surge
Operating Temperature Range
Storage Temperature Range — Plastic
— Ceramic
Symbol
VEE
VI
Iout
TA
Tstg
Rating
–8.0 to 0
0 to VEE
50
100
0 to +75
–55 to +150
–55 to +165
Unit
Vdc
Vdc
mA
°C
°C
MC10H016
L SUFFIX
CERAMIC PACKAGE
CASE 620–10
P SUFFIX
PLASTIC PACKAGE
CASE 648–08
FN SUFFIX
PLCC
CASE 775–02
ELECTRICAL CHARACTERISTICS
(VEE = –5.2 V
±5%)
(See Note)
0°
Characteristic
Power Supply Current
Input Current High
All Except MR
Pin 12 MR
Input Current Low
High Output Voltage
Low Output Voltage
High Input Voltage
Low Input Voltage
Symbol
IE
IinH
—
—
IinL
VOH
VOL
VIH
VIL
0.5
–1.02
–1.95
–1.17
–1.95
450
1190
—
–0.84
–1.63
–0.84
–1.48
—
—
0.5
–0.98
–1.95
–1.13
–1.95
265
700
—
–0.81
–1.63
–0.81
–1.48
—
—
0.3
–0.92
–1.95
–1.07
–1.95
265
700
—
–0.735
–1.60
–0.735
–1.45
µA
Vdc
Vdc
Vdc
Vdc
Min
—
Max
126
Min
—
25°
Max
115
Min
—
75°
Max
126
Unit
mA
µA
DIP
PIN ASSIGNMENT
VCC1
Q1
Q0
TC
PE
CE
PO
VEE
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
VCC2
Q2
Q3
CP
MR
P3
P2
P1
AC PARAMETERS
Propagation Delay
Clock to Q
Clock to TC
MR to Q
Set–up Time
Pn to Clock
CE or PE to Clock
Hold Time
Clock to Pn
Clock to CE or PE
Counting Frequency
Rise Time
Fall Time
tpd
1.0
0.7
0.7
tset
2.0
2.5
thold
1.0
0.5
fcount
tr
tf
200
0.5
0.5
—
—
—
2.0
2.0
1.0
0.5
200
0.5
0.5
—
—
—
2.1
2.1
1.0
0.5
200
0.5
0.5
—
—
—
2.2
2.2
MHz
ns
ns
—
—
2.0
2.5
—
—
2.0
2.5
—
—
ns
CE
L
H
L
H
X
X
2.4
2.4
2.4
1.0
0.7
0.7
2.5
2.5
2.5
1.0
0.7
0.7
2.7
2.6
2.6
ns
ns
Pin assignment is for Dual–in–Line Package.
For PLCC pin assignment, see the Pin Conversion
Tables on page 6–11 of the Motorola MECL Data
Book (DL122/D).
TRUTH TABLE
PE
L
L
H
H
X
X
MR
L
L
L
L
L
H
CP
Z
Z
Z
Z
ZZ
X
Function
Load Parallel (Pn to Qn)
Load Parallel (Pn to Qn)
Count
Hold
Masters Respond;
Slaves Hold
Reset (Qn = LOW,
TC = HIGH)
NOTE:
Each MECL 10H series circuit has been designed to meet the dc specifications shown in the test table,
after thermal equilibrium has been established. The circuit is in a test socket or mounted on a printed circuit
board and transverse air flow greater than 500 Ifpm is maintained. Outputs are terminated through a
50–ohm resistor to –2.0 volts.
Z = Clock Pulse (Low to High); ZZ = Clock Pulse (High to Low)
Features include assertion inputs and outputs on each
of the four master/slave counting flip–flops. Terminal
count is generated internally in a manner that allows
synchronous loading at nearly the speed of the basic
counter.
9/96
©
Motorola, Inc. 1996
2–1
REV 6
MOTOROLA [ MOTOROLA, INC ]
