MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
MC14094B
8-Stage Shift/Store Register
with Three-State Outputs
The MC14094B combines an 8–stage shift register with a data latch for
each stage and a three–state output from each latch.
Data is shifted on the positive clock transition and is shifted from the
seventh stage to two serial outputs. The QS output data is for use in
high–speed cascaded systems. The Q′S output data is shifted on the
following negative clock transition for use in low–speed cascaded systems.
Data from each stage of the shift register is latched on the negative
transition of the strobe input. Data propagates through the latch while strobe
is high.
Outputs of the eight data latches are controlled by three–state buffers
which are placed in the high–impedance state by a logic Low on Output
Enable.
•
Three–State Outputs
•
Capable of Driving Two Low–Power TTL Loads or One Low–Power
Schottky TTL Load Over the Rated Temperature Range
•
Input Diode Protection
•
Data Latch
•
Dual Outputs for Data Out on Both Positive and Negative Clock
Transitions
•
Useful for Serial–to–Parallel Data Conversion
•
Pin–for–Pin Compatible with CD4094B
MAXIMUM RATINGS*
(Voltages Referenced to VSS)
Symbol
VDD
Parameter
DC Supply Voltage
MC14XXXBCP
MC14XXXBCL
MC14XXXBD
L SUFFIX
CERAMIC
CASE 620
P SUFFIX
PLASTIC
CASE 648
D SUFFIX
SOIC
CASE 751B
ORDERING INFORMATION
Plastic
Ceramic
SOIC
TA = – 55° to 125°C for all packages.
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Î
Î
Î
ÎÎÎ
Î
Î
Î
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Î
Î
Î
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Î
Î
Î
ÎÎÎ
Î
Î
Î
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Î
Î
Î
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Î
Î
Î
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Î
Î
Î
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Î
Î
Î
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Î
Î
Î
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Î
Î
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Î
Î
Î
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Î
Î
Î
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Î
Î
Î
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Î
Î
Î
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Î
Î
Î
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Î
Î
Î
ÎÎÎ
ÎÎÎÎÎÎÎÎ
Î
Î
Î
Î
Î
Î
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Î
Î
Î
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Î
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Î
Î
Î
Î
Î
Î
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Î
Î
ÎÎÎ
Î
Î
Î
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Î
Î
Î
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Î
Î
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Î
Î
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Value
Unit
V
V
– 0.5 to + 18.0
±
10
500
Vin, Vout
Iin, Iout
PD
TL
Input or Output Voltage (DC or Transient)
– 0.5 to VDD + 0.5
Input or Output Current (DC or Transient),
per Pin
Power Dissipation, per Package†
Storage Temperature
mA
mW
Tstg
– 65 to + 150
260
PIN ASSIGNMENT
STROBE
DATA
CLOCK
Q1
Q2
Q3
Q4
VSS
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
VDD
OUTPUT
ENABLE
Q5
Q6
Q7
Q8
Q′S
QS
_
C
_
C
Lead Temperature (8–Second Soldering)
* Maximum Ratings are those values beyond which damage to the device may occur.
†Temperature Derating:
Plastic “P and D/DW” Packages: – 7.0 mW/
_
C From 65
_
C To 125
_
C
Ceramic “L” Packages: – 12 mW/
_
C From 100
_
C To 125
_
C
Output
Enable
0
0
1
1
1
1
Parallel Outputs
Strobe
X
X
0
1
1
1
Data
X
X
X
0
1
1
Q1
Z
Z
No Chg.
0
1
No Chg.
QN
Z
Z
No Chg.
QN–1
QN–1
No Chg.
Serial Outputs
QS*
Q7
No Chg.
Q7
Q7
Q7
No Chg.
Q′S
No Chg.
Q7
No Chg.
No Chg.
No Chg.
Q7
Clock
This device contains protection circuitry to
guard against damage due to high static
voltages or electric fields. However, pre-
cautions must be taken to avoid applications of
any voltage higher than maximum rated volt-
ages to this high–impedance circuit. For proper
operation, Vin and Vout should be constrained
to the range VSS
(Vin or Vout)
VDD.
Unused inputs must always be tied to an
appropriate logic voltage level (e.g., either VSS
or VDD). Unused outputs must be left open.
v
v
Z = High Impedance
X = Don’t Care
* At the positive clock edge, information in the 7th shift register stage is transferred to
Q8 and QS.
REV 3
1/94
©
MOTOROLA CMOS LOGIC DATA
Motorola, Inc. 1995
MC14094B
1
MOTOROLA [ MOTOROLA, INC ]
