CS
LOW
LEVEL
D9
HIGH
IMPEDANCE
D out
D9 – MSB
D8
D7
D6
D5
D4
D3
D2
D1
D0
SCLK
1
SAMPLE ANALOG INPUT
D in
A3
A2
A1
A0
2
3
4
5
6
7
8
9
10
11
16
1
A3
EOC
SHIFT IN NEW MUX ADDRESS,
SIMULTANEOUSLY SHIFT OUT PREVIOUS CONVERSION VALUE
INITIALIZE
A/D CONVERSION
INTERVAL
RE-INITIALIZE
MOTOROLA WIRELESS SEMICONDUCTOR
SOLUTIONS DEVICE DATA
Figure 11. Timing for 11- to 16-Clock Transfer Using CS* (Serial Transfer Interval Shorter than Conversion)
MUST BE HIGH ON POWER UP
D8
D7
D6
D5
D4
D3
D2
D1
D0
LOW LEVEL
1
SAMPLE ANALOG INPUT
A3
MSB
A2
A1
A0
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
SHIFT IN NEW MUX ADDRESS,
SIMULTANEOUSLY SHIFT OUT PREVIOUS CONVERSION VALUE
A/D CONVERSION INTERVAL
CS
D out
D9 – MSB
D9
SCLK
1
D in
A3
EOC
INITIALIZE
Figure 12. Timing for 16-Clock Transfer Not Using CS* (Serial Transfer Interval Shorter Than Conversion)
MC145053
9
NOTES:
D9, D8, D7, . . . , D0 = the result of the previous A/D conversion.
A3, A2, A1, A0 = the mux address for the next A/D conversion.
*This figure illustrates the behavior of the MC145051. The MC145050 behaves identically except there is no EOC signal and the conversion time is 44 ADCLK cycles (user-controlled time).
MOTOROLA [ MOTOROLA, INC ]
