MC145151–2 BLOCK DIAGRAM
RA2
RA1
RA0
OSCout
14 x 8 ROM REFERENCE DECODER
14
LOCK
DETECT
LD
OSCin
14–BIT
÷
R COUNTER
PHASE
DETECTOR
A
PDout
fin
VDD
14–BIT
÷
N COUNTER
14
PHASE
DETECTOR
B
φ
V
φ
R
fV
N13
N11
N9
N7 N6
N4
N2
N0
T/R
TRANSMIT OFFSET ADDER
NOTE: N0 – N13 inputs and inputs RA0, RA1, and RA2 have pull–up resistors that are not shown.
PIN DESCRIPTIONS
INPUT PINS
fin
Frequency Input (Pin 1)
Input to the
÷
N portion of the synthesizer. fin is typically
derived from loop VCO and is ac coupled into the device. For
larger amplitude signals (standard CMOS logic levels) dc
coupling may be used.
RA0 – RA2
Reference Address Inputs (Pins 5, 6, 7)
These three inputs establish a code defining one of eight
possible divide values for the total reference divider, as
defined by the table below.
Pull–up resistors ensure that inputs left open remain at a
logic 1 and require only a SPST switch to alter data to the
zero state.
Reference Address Code
RA2
0
0
0
0
1
1
1
1
RA1
0
0
1
1
0
0
1
1
RA0
0
1
0
1
0
1
0
1
Total
Divide
Value
8
128
256
512
1024
2048
2410
8192
sure that inputs left open remain at a logic 1 and require only
an SPST switch to alter data to the zero state.
T/R
Transmit/Receive Offset Adder Input (Pin 21)
This input controls the offset added to the data provided at
the N inputs. This is normally used for offsetting the VCO
frequency by an amount equal to the IF frequency of the
transceiver. This offset is fixed at 856 when T/R is low and
gives no offset when T/R is high. A pull–up resistor ensures
that no connection will appear as a logic 1 causing no offset
addition.
OSCin, OSCout
Reference Oscillator Input/Output (Pins 27, 26)
These pins form an on–chip reference oscillator when con-
nected to terminals of an external parallel resonant crystal.
Frequency setting capacitors of appropriate value must be
connected from OSC in to ground and OSC out to ground.
OSC in may also serve as the input for an externally–gener-
ated reference signal. This signal is typically ac coupled to
OSC in, but for larger amplitude signals (standard CMOS
logic levels) dc coupling may also be used. In the external
reference mode, no connection is required to OSC out.
OUTPUT PINS
PDout
Phase Detector A Output (Pin 4)
Three–state output of phase detector for use as loop–error
signal. Double–ended outputs are also available for this pur-
pose (see
φ
V and
φ
R).
Frequency fV > fR or fV Leading: Negative Pulses
Frequency fV < fR or fV Lagging: Positive Pulses
Frequency f V = fR and Phase Coincidence: High–Imped-
ance State
N0 – N11
N Counter Programming Inputs (Pins 11 – 20, 22 – 25)
These inputs provide the data that is preset into the
÷
N
counter when it reaches the count of zero. N0 is the least sig-
nificant and N13 is the most significant. Pull–up resistors en-
MOTOROLA
MC145151–2 through MC145158–2
3
MOTOROLA [ MOTOROLA, INC ]
