Order this document by MC145193/D
MC145193
1.1 GHz PLL Frequency
Synthesizer
The MC145193 is recommended for new designs and offers reduced
power consumption. The counters are programmed via a synchronous serial
port which is SPI compatible. The serial port is byte-oriented to facilitate
control via an MCU. Due to the innovative BitGrabber Plus™ registers, the
MC145193 may be cascaded with other peripherals featuring BitGrabber
Plus without requiring leading dummy bits or address bits in the serial data
stream. In addition, BitGrabber Plus peripherals may be cascaded with
existing BitGrabber™ peripherals.
The device features a single–ended current source/sink phase detector A
output and a double–ended phase detector B output. Both phase detectors
have linear transfer functions (no dead zones). The maximum current of the
single–ended phase detector output is determined by an external resistor
tied from the Rx pin to ground. This current can be varied via the serial port.
Slew–rate control is provided by a special driver designed for the REFout
pin. This minimizes interference caused by REFout.
This part includes a differential RF input that may be operated in a
single–ended mode. Also featured are on–board support of an external
crystal and a programmable reference output. The R, A, and N counters are
fully programmable. The C register (configuration register) allows the part to
be configured to meet various applications. A patented feature allows the C
register to shut off unused outputs, thereby minimizing system noise and
interference.
In order to have consistent lock times and prevent erroneous data from
being loaded into the counters, on–board circuitry synchronizes the update
of the A register if the A or N counters are loading. Similarly, an update of the
R register is synchronized if the R counter is loading.
The double–buffered R register allows new divide ratios to be presented
to the three counters (R, A, and N) simultaneously.
PLL FREQUENCY
SYNTHESIZER
SEMICONDUCTOR
TECHNICAL DATA
20
1
F SUFFIX
PLASTIC PACKAGE
CASE 751J
(SO–20)
PIN CONNECTIONS
REFout
LD
φ
R
φ
V
VPD
PDout
Gnd
Rx
Test 1
1
2
3
4
5
6
7
8
9
20 REFin
19 Din
18 CLK
17 ENB
16 Output A
15 Output B
14 VDD
13 Test 2
12 VCC
11 fin
(Top View)
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Maximum Operating Frequency: 1100 MHz @ – 10 dBm
Operating Supply Current: 3 mA Nominal at 3.0 V
Operating Supply Voltage Range (VDD, VCC, VPD Pins): 2.7 to 5.5 V
Current Source/Sink Phase Detector Output:
1.7 mA @ 5.0 V or 1.0 mA @ 3.0 V
Gain of Current Source/Sink Phase/Frequency Detector Controllable via
Serial Port
R Counter Division Range: 1 and 5 to 8191
Dual–Modulus Capability Provides Total Division up to 262,143
High–Speed Serial Interface: 4 Mbps
Output A Pin, When Configured as Data Out, Permits Cascading of
Devices
Two General–Purpose Digital Outputs:
Output A: Totem–Pole (Push–Pull) with Four Output Modes
Output B: Open–Drain
Patented Power–Saving Standby Feature with Orderly Recovery for
Minimizing Lock Times, Standby Current: 30
µA
See App Note AN1253/D for Low–Pass Filter Design, and AN1277/D for
Offset Reference PLLs for Fine Resolution or Fast Hopping
fin 10
EVALUATION KIT
The MC145193EVK, which contains
hardware and software, is available.
ORDERING INFORMATION
Device
MC145193F
Operating
Temperature Range
TA = –40 to 85°C
Package
SO–20
BitGrabber and BitGrabber Plus are trademarks of Motorola, Inc.
©
Motorola, Inc. 2000
Rev 1
MOTOROLA WIRELESS SEMICONDUCTOR
SOLUTIONS – RF AND IF DEVICE DATA
1
MOTOROLA [ MOTOROLA, INC ]
