PIN DESCRIPTIONS
1
VDD
14
DI1
16
VCC
Tx1
3
VDD
Positive Power Supply (Pin 1)
The most positive power supply pin, which is typically + 5
to + 12V.
12 DI2
Tx2 5
Vin =
±
2 V
VSS
Negative Power Supply (Pin 8)
The most negative power supply pin, which is typically – 5
to – 12 V.
VCC
Digital Power Supply (Pin 16)
The digital supply pin, which is connected to the logic
power supply (maximum + 5.5 V). V CC
must
be less than
or equal to V DD .
GND
Ground (Pin 9)
Ground return pin is typically connected to the signal
ground pin of the EIA 232–E connector (Pin 7) as well as to
the logic power supply ground.
10
DI3
Tx3
7
VSS GND
8
9
Vin
Rout =
I
Figure 1. Power–Off Source Resistance (Drivers)
DRIVERS
3V
DI1–DI3
50%
0V
tf
Tx1–Tx3
tPHL
90%
10%
tPLH
tr
VOH
VOL
Rx1, Rx2, Rx3
Receive Data Input (Pins 2, 4, 6)
These are the EIA 232–E receive signal inputs whose
voltages can range from (VDD + 15 V) to (VSS – 15 V). A volt-
age between + 3 and (VDD + 15 V) is decoded as a space
and causes the corresponding DO pin to swing to ground (0
V); a voltage between – 3 and (VDD – 15 V) is decoded as a
mark and causes the DO pin to swing up to VCC. The actual
turn–on input switchpoint is typically biased at 1.8 V above
ground, and includes 800mV of hysteresis for noise rejec-
tion. The nominal input impedance is 5 kΩ. An open or
grounded input pin is interpreted as a mark, forcing the DO
pin to VCC.
DO1, DO2, DO3
Data Output (Pins 11, 13, 15)
These are the receiver digital output pins, which swing
from VCC to GND. A space on the Rx pin causes DO to pro-
duce a logic 0; a mark produces a logic 1. Each output pin is
capable of driving one LSTTL input load.
DI1, DI2, DI3
Data Input (Pins 10, 12,14)
These are the high–impedance digital input pins to the
drivers. TTL compatibility is accomplished by biasing the in-
put switchpoint at 1.4 V above GND. However, 5–V CMOS
compatibility is maintained as well. Input voltage levels on
these pins must be between VCC and GND.
Tx1, Tx2, Tx3
Transmit Data Output(Pins 3, 5, 7)
These are the EIA 232–E transmit signal output pins,
which swing toward VDD and VSS. A logic 1 at a DI input
causes the corresponding Tx output to swing toward VSS. A
logic 0 causes the output to swing toward VDD (the output
voltages will be slightly less than VDD or VSS depending upon
the output load). Output slew rates are limited to a maximum
of 30 V per
µs.
When the MC145406 is off (VDD = VSS = VCC
= GND), the minimum output impedance is 300
Ω.
RECEIVERS
+3V
Rx1–Rx3
50%
0V
tPHL
90%
DO1–DO3
50%
10%
tf
tr
tPLH
VOH
VOL
Figure 2. Switching Characteristics
DRIVERS
Tx1–Tx3
tSLH
SLEW RATE (SR) =
3V
–3V
3V
–3V
tSHL
– 3 V – (3 V)
3 V – ( – 3 V)
OR
tSLH
tSHL
Figure 3. Slew–Rate Characterization
MC145406
4
MOTOROLA
MOTOROLA [ MOTOROLA, INC ]
