PIN DESCRIPTIONS
17
19
VDD VCC
15
DI1
Tx1
6
VCC
Digital Power Supply (Pin 19)
The digital supply pin, which is connected to the logic pow-
er supply. This pin should have a 0.33
µF
capacitor to
ground.
GND
Ground (Pin 2)
13 DI2
Tx2 8
Vin =
±
2 V
11
DI3
Tx3
10
Ground return pin is typically connected to the signal
ground pin of the EIA–232–E connector (Pin 7) as well as to
the logic power supply ground.
Vin
Rout =
I
VSS GND
4
2
VDD
Positive Power Supply (Pin 17)
This is the positive output of the on–chip voltage doubler
and the positive power supply input of the driver/receiver
sections of the device. This pin requires an external storage
capacitor to filter the 50% duty cycle voltage generated by
the charge pump.
VSS
Negative Power Supply (Pin 4)
Figure 1. Power–Off Source Resistance
DRIVERS
DI1 – DI3
50%
3V
0V
tf
tr
VOH
10%
tPHL
tPLH
VOL
This is the negative output of the on–chip voltage doubler/
inverter and the negative power supply input of the driver/re-
ceiver sections of the device. This pin requires an external
storage capacitor to filter the 50% duty cycle voltage gener-
ated by the charge pump.
C2+, C2–, C1–, C1+
Voltage Doubler and Inverter (Pins 1, 3, 18, 20)
These are the connections to the internal voltage doubler
and inverter, which generate the VDD and VSS voltages.
Rx1, Rx2, Rx3
Receive Data Input (Pins 5, 7, 9)
Tx1 – Tx3
90%
RECEIVERS
+3V
Rx1 – Rx3
50%
0V
tPHL
90%
DO1 – DO3
50%
10%
tf
tr
tPLH
VOH
VOL
These are the EIA–232–E receive signal inputs. A voltage
between + 3 and + 25 V is decoded as a space and causes
the corresponding DO pin to swing to ground (0 V). A voltage
between – 3 and – 25 V is decoded as a mark, and causes
the DO pin to swing up to VCC.
DO1, DO2, DO3
Data Output (Pins 16, 14, 12)
These are the receiver digital output pins, which swing
from VCC to GND. Each output pin is capable of driving one
LSTTL input load.
DI1, DI2, DI3
Data Input (Pins 15, 13, 11)
These are the high impedance digital input pins to the driv-
ers. Input voltage levels on these pins must be between VCC
and GND.
Figure 2. Switching Characteristics
DRIVERS
3V
Tx1 – Tx3
–3V
tSLH
SLEW RATE (SR) =
3V
–3V
tSHL
– 3 V – (3 V)
3 V – ( – 3 V)
OR
tSLH
tSHL
Tx1, Tx2, Tx3
Transmit Data Output (Pins 6, 8, 10)
These are the EIA–232–E transmit signal output pins,
which swing toward VDD and VSS. A logic 1 at a DI input
causes the corresponding Tx output to swing toward VSS. A
logic 0 causes the output to swing toward VDD. The actual
levels and slew rate achieved will depend on the output load-
ing (RL
ø
CL).
Figure 3. Slew Rate Characterization
MOTOROLA
MC145407
5
MOTOROLA [ MOTOROLA, INC ]
