MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Order this document
by MC145532/D
ADPCM Transcoder
MC145532
16
1
Conforms to G.721–1988 and T1.301–1987
The MC145532 Adaptive Differential Pulse Code Modulation (ADPCM)
Transcoder provides a low–cost, full–duplex, single–channel transcoder to
(from) a 64 kbps PCM channel from (to) either a 16 kbps, 24 kbps, 32 kbps, or
64 kbps channel.
•
•
•
•
•
•
•
•
•
•
•
•
•
Complies with CCITT Recommendation G.721–1988
Complies with the American National Standard (T1.301–1987)
Full–Duplex, Single–Channel Operation
Mu–Law or A–Law Coding is Pin Selectable
Synchronous or Asynchronous Operation
Easily Interfaces with Any Member of Motorola’s PCM Codec–Filter
Mono–Circuit Family or Other Industry Standard Codec
Serial PCM and ADPCM Data Transfer Rate from 64 kbps to 5.12 Mbps
Power–Down Capability for Low Current Consumption
The Reset State, an Option Specified in the Standards, is Automatically
Initiated When the RESET Pin is Released
Simple Time Slot Assignment Timing for Transcoder Applications
Single 5 V Power Supply
16–Pin Package
The MC145536EVK is the Evaluation Platform for the MC145532 and Also
Includes the MC145480 5 V PCM Codec–Filter
DW SUFFIX
SOG PACKAGE
CASE 751G
16
1
L SUFFIX
CERAMIC PACKAGE
CASE 620
ORDERING INFORMATION
MC145532DW SOG Package
MC145532L
Ceramic Package
PIN ASSIGNMENT
MODE
DDO
DOE
DDC
DDI
DIE
RESET
VSS
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
VDD
EDO
EOE
EDC
EDI
EIE
SPC
APD
BLOCK DIAGRAM
DDO
DOE
S REG
DDC
DDI
DIGITAL
SIGNAL
PROCESSOR
REG
LATCH
S REG
EDC
EDI
I/O DATA BUS
EDO
EDE
S REG
DIE
LATCH
REG
S REG
EIE
MODE
APD
VSS
RESET
SPC
VDD
REV 1
9/95 (Replaces NP470)
©
Motorola, Inc. 1995
MOTOROLA
MC145532
1
MOTOROLA [ MOTOROLA, INC ]
