ASYNC BUS
PERIPHERAL
1
FC
SIZ
CLKOUT
AS
SIZ
CLK
AS
DSACK
DS
DSACK
DS
CS
CS3
CS5
IACK
IRQ
ADDR[23:0]
DATA[15:0]
IRQ
ADDR[15:0]
DATA[15:0]
2
MEMORY
2
MCU
ADDR[23:0]
DATA[15:8]
CS
R/W
CSBOOT
R/W
4
MEMORY
2
ADDR[23:0]
DATA[7:0]
CS
R/W
1. Can be decoded to provide additional address space.
2. Varies depending upon peripheral memory size.
32 EXAMPLE SYS BLOCK
Figure 4-17 Basic MCU System
Chip-select assertion can be synchronized with bus control signals to provide output
enable, read/write strobe, or interrupt acknowledge signals. Chip select logic can also
generate DSACK and AVEC signals internally. Each signal can also be synchronized
with the ECLK signal available on ADDR23.
When a memory access occurs, chip-select logic compares address space type, ad-
dress, type of access, transfer size, and interrupt priority (in the case of interrupt ac-
knowledge) to parameters stored in chip-select registers. If all parameters match, the
appropriate chip-select signal is asserted. Select signals are active low. If a chip-select
function is given the same address as a microcontroller module or an internal memory
array, an access to that address goes to the module or array, and the chip-select sig-
nal is not asserted. The external address and data buses do not reflect the internal ac-
cess.
All chip-select circuits are configured for operation out of reset. However, all chip-se-
lect signals except CSBOOT are disabled, and cannot be asserted until the BYTE field
in the corresponding option register is programmed to a nonzero value, selecting a
MC68331
SYSTEM INTEGRATION MODULE
MOTOROLA
4-49
USER’S MANUAL
MOTOROLA [ MOTOROLA ]
