MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
8-Bit Serial-Input/Serial or
Parallel-Output Shift Register
with Latched 3-State Outputs
High–Performance Silicon–Gate CMOS
The MC54/74HC595A is identical in pinout to the LS595. The device
inputs are compatible with standard CMOS outputs; with pullup resistors,
they are compatible with LSTTL outputs.
The HC595A consists of an 8–bit shift register and an 8–bit D–type latch
with three–state parallel outputs. The shift register accepts serial data and
provides a serial output. The shift register also provides parallel data to the
8–bit latch. The shift register and latch have independent clock inputs. This
device also has an asynchronous reset for the shift register.
The HC595A directly interfaces with the Motorola SPI serial data port on
CMOS MPUs and MCUs.
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Output Drive Capability: 15 LSTTL Loads
Outputs Directly Interface to CMOS, NMOS, and TTL
Operating Voltage Range: 2.0 to 6.0 V
Low Input Current: 1.0
µA
High Noise Immunity Characteristic of CMOS Devices
In Compliance with the Requirements Defined by JEDEC Standard
No. 7A
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Chip Complexity: 328 FETs or 82 Equivalent Gates
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Improvements over HC595
— Improved Propagation Delays
— 50% Lower Quiescent Power
— Improved Input Noise and Latchup Immunity
MC54/74HC595A
J SUFFIX
CERAMIC PACKAGE
CASE 620–10
1
16
16
1
N SUFFIX
PLASTIC PACKAGE
CASE 648–08
16
1
D SUFFIX
SOIC PACKAGE
CASE 751B–05
16
1
DT SUFFIX
TSSOP PACKAGE
CASE 948F–01
ORDERING INFORMATION
MC54HCXXXAJ
MC74HCXXXAN
MC74HCXXXAD
MC74HCXXXADT
Ceramic
Plastic
SOIC
TSSOP
LOGIC DIAGRAM
SERIAL
DATA
INPUT
14
15
1
2
PIN ASSIGNMENT
QB
QA
QB
PARALLEL
DATA
OUTPUTS
QC
QD
QE
QF
QG
QH
GND
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
VCC
QA
A
OUTPUT ENABLE
LATCH CLOCK
SHIFT CLOCK
RESET
SQH
A
SHIFT
REGISTER
LATCH
QC
3
QD
4
QE
5
QF
6
QG
7
QH
SHIFT 11
CLOCK
10
RESET
LATCH 12
CLOCK
OUTPUT 13
ENABLE
VCC = PIN 16
GND = PIN 8
9
SQH
SERIAL
DATA
OUTPUT
10/95
©
Motorola, Inc. 1995
1
REV 6
MOTOROLA [ MOTOROLA, INC ]
