Order this document by SG3525A/D
Pulse Width
Modulator Control Circuits
The SG3525A, SG3527A pulse width modulator control circuits offer
improved performance and lower external parts count when implemented for
controlling all types of switching power supplies. The on–chip +5.1 V
reference is trimmed to
±1%
and the error amplifier has an input
common–mode voltage range that includes the reference voltage, thus
eliminating the need for external divider resistors. A sync input to the
oscillator enables multiple units to be slaved or a single unit to be
synchronized to an external system clock. A wide range of deadtime can be
programmed by a single resistor connected between the CT and Discharge
pins. These devices also feature built–in soft–start circuitry, requiring only an
external timing capacitor. A shutdown pin controls both the soft–start circuitry
and the output stages, providing instantaneous turn off through the PWM
latch with pulsed shutdown, as well as soft–start recycle with longer
shutdown commands. The under voltage lockout inhibits the outputs and the
changing of the soft–start capacitor when VCC is below nominal. The output
stages are totem–pole design capable of sinking and sourcing in excess of
200 mA. The output stage of the SG3525A features NOR logic resulting in a
low output for an off–state while the SG3527A utilized OR logic which gives a
high output when off.
•
8.0 V to 35 V Operation
SG3525A
SG3527A
PULSE WIDTH MODULATOR
CONTROL CIRCUITS
SEMICONDUCTOR
TECHNICAL DATA
16
1
N SUFFIX
PLASTIC PACKAGE
CASE 648
•
•
•
•
•
•
•
•
5.1 V
±
1.0% Trimmed Reference
100 Hz to 400 kHz Oscillator Range
Separate Oscillator Sync Pin
Adjustable Deadtime Control
Input Undervoltage Lockout
Latching PWM to Prevent Multiple Pulses
Pulse–by–Pulse Shutdown
Dual Source/Sink Outputs:
±400
mA Peak
16
1
DW SUFFIX
PLASTIC PACKAGE
CASE 751B
(SO–16L)
PIN CONNECTIONS
Inv. Input
Noninv. Input
Sync
OSC. Output
1
2
3
4
5
6
7
8
(Top View)
16 Vref
15 VCC
14 Output B
13 VC
12 Ground
11 Output A
10 Shutdown
9
Compensation
Representative Block Diagram
CT
16
Vref
15
VCC
12
Ground
OSC Output
Sync
RT
CT
Discharge
Compensation
INV. Input
2
Noninv. Input
8
CSoft–Start
10
Shutdown
5.0k
Output B
5.0k
OR
14
4
3
6
5
7
R
9
1
–
Error
Amp
+
+
– PWM
–
50µA
VREF
S
Latch
S
OR
SG3525A Output Stage
13
VC
Output A
11
Oscillator
F/F
Q
Q
NOR
14
Output B
Reference
Regulator
To Internal
Circuitry
Under–
Voltage
Lockout
NOR
VC
13
Output A
11
RT
Discharge
Soft–Start
ORDERING INFORMATION
Device
SG3525AN
SG3525ADW
TA = 0° to +70°C
Operating
Temperature Range
Package
Plastic DIP
SO–16L
Plastic DIP
Rev 2
SG3527A
Output Stage
SG3527AN
©
Motorola, Inc. 1996
MOTOROLA ANALOG IC DEVICE DATA
1