SN54/74LS174
HEX D FLIP-FLOP
The LSTTL / MSI SN54 / 74LS174 is a high speed Hex D Flip-Flop. The
device is used primarily as a 6-bit edge-triggered storage register. The
information on the D inputs is transferred to storage during the LOW to HIGH
clock transition. The device has a Master Reset to simultaneously clear all
flip-flops. The LS174 is fabricated with the Schottky barrier diode process for
high speed and is completely compatible with all Motorola TTL families.
HEX D FLIP-FLOP
LOW POWER SCHOTTKY
•
•
•
•
Edge-Triggered D-Type Inputs
Buffered-Positive Edge-Triggered Clock
Asynchronous Common Reset
Input Clamp Diodes Limit High Speed Termination Effects
CONNECTION DIAGRAM DIP
(TOP VIEW)
VCC
16
Q5
15
D5
14
D4
13
Q4
12
D3
11
Q3
10
CP
9
NOTE:
The Flatpak version
has the same pinouts
(Connection Diagram) as
the Dual In-Line Package.
16
16
1
J SUFFIX
CERAMIC
CASE 620-09
N SUFFIX
PLASTIC
CASE 648-08
1
1
MR
2
Q0
3
D0
4
D1
5
Q1
6
D2
7
Q2
8
GND
PIN NAMES
LOADING
(Note a)
16
HIGH
D0 – D5
CP
MR
Q0 – Q5
Data Inputs
Clock (Active HIGH Going Edge) Input
Master Reset (Active LOW) Input
Outputs (Note b)
0.5 U.L.
0.5 U.L.
0.5 U.L.
10 U.L.
LOW
0.25 U.L.
0.25 U.L.
0.25 U.L.
5 (2.5) U.L.
1
D SUFFIX
SOIC
CASE 751B-03
ORDERING INFORMATION
SN54LSXXXJ
SN74LSXXXN
SN74LSXXXD
Ceramic
Plastic
SOIC
NOTES:
a. 1 TTL Unit Load (U.L.) = 40
µA
HIGH/1.6 mA LOW.
b. The Output LOW drive factor is 2.5 U.L. for Military (54) and 5 U.L. for Commercial (74)
b.
Temperature Ranges.
LOGIC SYMBOL
LOGIC DIAGRAM
3 4 6 11 13 14
MR CP D5
1
9
14
D4
13
D3
11
D2
6
D1
4
D0
3
9
1
D Q
CP
CD
15
D Q
CP
CD
12
D Q
CP
CD
10
D Q
CP
CD
7
D Q
CP
CD
5
D Q
CP
CD
D0 D1 D2 D3 D4 D5
CP
MR
Q0 Q1 Q2 Q3 Q4 Q5
2 5 7 10 12 15
2
VCC = PIN 16
GND = PIN 8
= PIN NUMBERS
Q5
Q4
Q3
Q2
Q1
Q0
VCC = PIN 16
GND = PIN 8
FAST AND LS TTL DATA
5-1
MOTOROLA [ MOTOROLA, INC ]
