PWM Output Current Control
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An LED operates at its maximum efficiency when
operated at the rated drive current specified by
the manufacturer. Operating an LED at lower than
its rated forward current not only decreases the
system efficiency; but may cause color (or wave-
length) shifting. In illumination applications, this
could cause visible changes to lighting.
A preferred method is using pulse width modula-
tion (PWM). As shown at left, the output current
is adjusted by applying a PWM signal to the V
ADJ
input. By varying the signal duty cycle the average
output current is adjusted up or down. To avoid
visible flicker, the PWM signal should be greater
than 100 Hz.
For duty cycles (DPWM) between 0 and 1, the
output current is derived by the formula:
PWM Control Signals
I
NOM
= I
MAX
X D
PWM
The V
ADJ
input may be driven via an open collec-
tor transistor (as shown). The diode and resistor
suppress high amplitude negative spikes that may
be caused by the drain-source capacitance of the
transistor. Negative spikes on the control input of
the unit could cause errors in output current or
erratic operation.
The V
ADJ
input can also be driven by the open drain
output of a microcontroller. Again, any high amplitude
negative spikes that may be caused by the drain-
source capacitance of the FET must be supressed.
PWM Dimming Application
Get a full explanation
of this circuit in “Driving
LEDs”.
Available free at the
MPD
website
A simple method of achieving digital (or PWM) dimming is by using a 555 timer
to apply a series of pulses to the V
ADJ
input, as illustrated above. The 555 oper-
ates over a supply voltage range of 4.5 VDC to 15VDC. Here it is connected
to the 12 VDC output of the
SR7805
switching regulator (this is also the V
IN
of the LED driver). Care should be taken to minimize ripple at the V
CC
input.
Excess ripple could cause timing errors.
again. The formulas for calculating the frequency and duty cycle are included
in the MPD application note “Driving
LEDs”.
The diodes (D
1
and D
2
) allow duty cycles below 50% to be set. Diode D
1
bypasses R
2
while C
4
is charging. Diode D
2
is optional (but recommended),
essentially blocking R
2
during the charge period. Theoretically, this circuit will
allow for duty cycles over a range of approximately 5% to 95%. If manual
The timer is connected for astable (free run) operation. The frequency is set adjustment is desired, a potentiometer may be substituted for R
2
(with some
by R
1
, R
2
and C
4
. The timing capacitor (C
4
) charges through R
1
and D
2
. When adjustment of the circuit).
it reaches the level of
2/3
V
CC
, the discharge pin (pin 7) goes low and C
4
will
discharge through D
1
and R
2
to the internal discharge transistor. When the C
4
The size of C
4
is generally not critical, but it should be as low leakage as pos-
voltage drops to
1/3
V
CC
, the discharge pin goes high and C
4
begins to charge sible. In order to avoid excessive current flow through the internal discharge
transistor, it is recommended that R
1
be at least 5 k .
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•
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•
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•
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