HF01B00/01/02/03/04–OFF LINE HIGH VOLTAGE QUASI RESONANT REGULATOR
Figure 5 shows the waveform of valley switching
detection on auxiliary winding and the MOSFET
Drain-Source voltage.
8.8us
VAUX
Valley point
45mV
VDS
Figure 7—Minimum Turn-off Time Limit
Over-voltage Protection (OVP)
The positive plateau of the auxiliary winding
voltage is proportional to the output voltage. The
Over Voltage Protection unit detects the auxiliary
winding voltage signal by VSD pin instead of
directly monitoring the output voltage.
Figure 5—Valley Switching Detection
An internal minimum off-time limiter prevents the
MOSFET from turning on until the 7.8us off-time
limit is passed.. Thus the minimum off time of
primary switch will be longer than 7.8us and the
switching frequency would be lower than
1/(Ton+7.8us). This ensures that the switching
frequency is below 150kHz, which is below the
CISPER22 EMI minimum limit. Figure 6 and 7
shows the minimum turn-off time limit of the
primary switch.
Figure 8 shows the external circuit of VSD pin. If
the voltage of this pin exceeds 6V, the OVP is
triggered, and the HF01B00/01/02/03/04 stops
switching and goes into latched fault condition.
That means the regulator stays fully latched in
this position until the Vcc is decreased down to
3V, e.g. when the user unplugs the power supply
from the main supply and re-plugs it.
HF01B00-04
6.8us
ROVP
VSD
OVP
Auxiliary
RINT
Winding
6V
Figure 8—OVP Circuit
The internal resistance of VSD pin is 24kΩ, so
the OVP triggered point could be programmed
through different ROVP selection by the following
Figure 6—Minimum Turn-off Time Limit
formula:
N 6 R ROVP
N 6 24k R
OVP
S
INT
S
VOVP
NA RINT
NA 24k
HF01B00/01/02/03/04 Rev. 1.2
www.MonolithicPower.com
10
4/9/2013
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