MP2107/MP2107A – 4A, 6V SYNCHRONOUS STEP-DOWN SWITCHING REGULATOR
PIN FUNCTIONS
SOIC
Pin#
–
3
6, 7
2
4
1
QFN
Pin#
6
4, 7
3, 8
2, 9
5
1
Name
Description
Open Drain Power Good Output. “HIGH” output indicates V
OUT
is within ±10%
POK
window. “LOW” output indicates V
OUT
is out of ±10% window. POK is pulled down
in shutdown.
Input Supply. A decoupling capacitor to ground is required close to these pins to
IN
reduce switching spikes.
Switch Node Connection to the Inductor. These pins connect to the internal high
SW
and low-side power MOSFET switches. All SW pins must be connected together
externally.
Ground. Connect these pins with larger copper areas to the negative terminals of
GND
the input and output capacitors.
Bootstrap. A capacitor between this pin and SW provides a floating supply for the
BS
high-side gate driver.
Feedback. This is the input to the error amplifier. An external resistive divider
FB
connects this pin between the output and GND. The voltage on the FB pin
compares to the internal 0.8V reference to set the regulation voltage.
Enable and Frequency Synchronization Input Pin. Forcing this pin below 0.4V
shuts down the part. Forcing this pin above 1.6V turns on the part. Applying a
EN/SYNC
1MHz to 2MHz clock signal to this pin synchronizes the internal oscillator frequency
to the external clock.
Logic circuitry bias supply. Connect directly to VIN or 3.3V to 5V supply. Bypass
VCC
with a low ESR 1µF ceramic capacitor as close to the pin as possible
8
10
5
–
MP2107/MP2107A Rev. 1.1
www.MonolithicPower.com
10/13/2010
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© 2010 MPS. All Rights Reserved.
4
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