TM
MP6400 -- LOW QUIESCENT CURRENT PROGRAMMABLE-DELAY SUPERVISORY CIRCUIT
FUNCTIONAL BLOCK DIAGRAM
VCC
VCC
90k
MR
0.4V
Reset
Logic
Timer
MP6400DJ-01
Adjustable Voltage
RESET
VCC
90k
MR
SENSE
R1
R2
--
Reset
Logic
Timer
0.4V
C
DELAY
C
DELAY
MP6400DJ-XX
RESET
VCC
+
SENSE
--
+
GND
Adjustable Voltage Version
GND
Fixed Voltage Version
Figure 1—Functional Block Diagram
TIMING DIAGRAM
V
CC
0.8V
0.0V
RESET
t
D
SENSE
V
IT
+V
HYS
V
IT
t
D
t
D
t
D
=Reset Delay
=Undefined State
MR
0.7V
CC
0.25V
CC
Time
Figure 2—MP6400 Timing Diagram
TRUTH TABLE
SENSE > V
IT
0
1
0
1
M R
R E S E T
L
L
H
H
L
L
L
H
MP6400 Rev. 1.0
9/7/2012
www.MonolithicPower.com
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2012 MPS. All Rights Reserved.
8
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