TM
MP6400 -- LOW QUIESCENT CURRENT PROGRAMMABLE-DELAY SUPERVISORY CIRCUIT
APPLICATION INFORMATION
Reset Output Function
R E S E T
The MP6400
output is typically connected
R E S E T
to the
input of a microprocessor, as shown
R E S E T
in Figure 3. When
is not asserted, a pull
up resistor must be connected to hold this signal
high. The voltage of reset signal is allowed to be
higher than V
CC
(up to 6V) through a resistor
pulling up from supply line. If the voltage is below
R E S E T
0.8V,
output is undefined. This condition
can be ignored generally because that most
microprocessors do not
M
function at this state.
R
are higher than their
When both SENSE and
R E S E T
threshold voltage,
output holds logic high.
Once either of the two drops below their
R E S E T
threshold,
will be asserted.
V
CC
R1
VCC
connects to the SENSE pin. The circuit can be
used to monitor any voltage higher than 0.4V.
V
SEN
V
OUT
VCC
V
IT
= (1+
R1
R1
)0.4
R2
MP6400DJ-01
RESET
SENSE
1nF
R2
GND
Figure 4—MP6400DJ-01 Monitoring a User-
Defined Voltage
Monitor Multiple System Voltages
M R
The manual reset (
) can introduce another
M R
R E S E T
logic signal to control the
. When
is a
R E S E T
will be asserted. After
logic low (0.25V
CC
),
M R
are above their thresholds,
both SENSE and
R E S E T
will be driven to a logic high after a reset
M R
is internally connected to V
CC
delay time. The
through a 90kΩ resistor so this pin can float. See
how multiple system voltages are monitored by
M R
M R
in Figure 5. If the signal on
isn’t up to V
CC
,
there will be an additional current through internal
90kΩ pull up resistor. A logic-level FET can be
used to minimize the leakage, as shown in Figure
6.
1.2V
3.3V
Microprocessor
SENSE
100k
DSP
Microcontroller
0.1uF
1nF
R2
MR
RESET
47pF
RESET
GND
GND C
DELAY
C
DELAY
Figure 3—Typical Application of MP6400 with
Microprocessor
From the point that
is again logic high and
SENSE is above V
IT
+ V
HYS
(the threshold
R E S E T
hysteresis),
will be driven to a logic high
after a reset delay time. The reset delay time is
programmable by C
DELAY
pin. Due to the finite
R E S E T
impedance of
pin, the pull up resistor
should be bigger than 10kΩ.
Monitor a Voltage
The SENSE input pin is connected to the
monitored system voltage directly or through a
resistor network (on MP6400DJ-01). When the
R E S E T
voltage on the pin is below V
IT
,
is asserted.
A threshold hysteresis will prevent the chip from
responding perturbation on SENSE pin. A 1nF to
10nF bypass capacitor should be put on this pin
to increase its immunity to noise. A typical
application of the MP6400DJ-01 is shown in
Figure 4. Two external resistors form a voltage
divider from monitored voltage to GND. Its tap
MP6400 Rev. 1.0
9/7/2012
M R
SENSE VCC
SENSE VCC
V
I/O
V
CORE
MP6400DJ-12
RESET
C
DELAY
GND
MP6400DJ-33
MR
RESET
DSP
RESET
C
DELAY
GND
GND
Figure 5— MP6400 Family Monitoring Multiple
System Voltages
www.MonolithicPower.com
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2012 MPS. All Rights Reserved.
9
MPS [ MONOLITHIC POWER SYSTEMS ]
