NB650/NB650H – 6A, 28V, FAST-TRANSIENT, SYNCHRONOUS STEP-DOWN CONVERTERS
Where R
O
is the equivalent load resistor.
As described in Figure 6, V
SLOPE2
in skip mode is
smaller than V
SLOPE1
in PWM mode, so the jitter in
the skip mode is larger. For less jitter during
ultra-light–load conditions, select smaller V
FB
resistors, though at the cost of light-load
efficiency.
becomes the reference to the PWM comparator.
At this point, the soft-start finishes and it enters
steady-state operation.
When the EN pin goes low, a 10µA internal
current source discharges the SS capacitor.
Once the SS voltage reaches the REF voltage,
acts as the reference to the PWM comparator.
The output voltage decreases smoothly with the
SS voltage until it reaches zero level. Determine
the SS capacitor as follows:
VID Input
Typically, R1 and R2 set the output voltage with
V
FB
=0.6V. R2, in this case, is a combination of
R2A, R2B, and R2C depends on the VID, which
is active low. The NB650/NB650H can
dynamically track VID codes as they change. As
a result, the converter output voltage can change
without the need to reset either the controller or
the value of R1 and R2A. As shown in Figure 1,
R2B and R2C are parallel with R2A. The
equivalent value of R2 can change due to
different VID codes. One can get four V
OUT
values depending on the VID codes with the
details in the application information. The VID
logic and equivalent R2s are shown in Table 1.
Table 1: VID Logic
VID2
VID1
C
SS
(nF)
=
t
SS
(ms )
×
I
SS
(
μ
A )
V
REF
( V )
(12)
If the output capacitors have large capacitance
values, avoid setting a short SS time. Use a
minimum value of 4.7nF if the output capacitance
value exceeds 330µF.
Power Good
The NB650/NB650H has power-good (PG)
output. The PG pin is the open drain of a
MOSFET. Connect to V
CC
or another voltage
source through a resistor (e.g. 100kΩ). The
MOSFET turns ON after the application of the
input voltage so that the PG pin is pulled to GND
before the SS is ready. After the FB voltage
reaches 90% of the reference voltage, the PG pin
is pulled high after a delay.
R2
1
1
0
0
1
0
1
0
R
2
=
R
2A
R
2
=
R
2A
// R
2B
R
2
=
R
2A
// R
2C
R
2
=
R
2A
// R
2B
// R
2C
The PG delay is determined as follows:
Enable Control
The NB650/NB650H has a dedicated Enable
control pin (EN). Pulling this pin high or low
enables or disables the IC. Tie EN to V
IN
through
a resistor for automatic start-up.
Soft Start/Stop
The NB650/NB650H employs a soft-start/stop
(SS) mechanism to ensure smooth output during
power-up and power shutdown. When the EN pin
goes high, an internal current source (10μA)
charges up the SS capacitor. The SS capacitor
voltage then acts as the V
REF
voltage to the PWM
comparator. The output voltage smoothly ramps
up with the SS voltage. Once the SS voltage
reaches the same level as the REF voltage, it
continues ramping up while the REF voltage
t
PG
(ms )
=
4
×
t
SS
(ms )
9
(13)
When the FB voltage drops to 90% of the
reference voltage, the PG pin is pulled low.
Over-Current Protection and Short-Circuit
Protection
The NB650/NB650H has cycle-by-cycle over-
current limit control. The inductor current is
monitored during the ON state. Once the inductor
current hits the current limit, the HS-FET turns off.
At the same time, the over-current protection
(OCP) timer starts. The OCP timer is set as 50μs.
If the current limit is hit for every cycle within that
50μs period, then OCP will trigger.
When the output is shorted to ground, the device
hits its current limit and the FB voltage is less
than 0.4V. The device treats this as a dead-short
NB650/NB650H Rev. 1.12
www.MonolithicPower.com
10/11/2012
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2012 MPS. All Rights Reserved.
12
MPS [ MONOLITHIC POWER SYSTEMS ]
