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ADC-305-1 参数 Datasheet PDF下载

ADC-305-1图片预览
型号: ADC-305-1
PDF下载: 下载PDF文件 查看货源
内容描述: 8位, 20MHz的CMOS A / D转换器 [8-Bit, 20MHz CMOS A/D Converters]
分类和应用: 转换器光电二极管
文件页数/大小: 6 页 / 234 K
品牌: MURATA-PS [ MURATA POWER SOLUTIONS INC. ]
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www.murata-ps.com
ADC-305
8-Bit, 20MHz CMOS A/D Converters
PRODUCT OVERVIEW
OBSOLETE PRODUCT
Contact Factory for Replacement Model
DATEL's ADC-305 is an 8-bit, 20MHz sam-
pling, CMOS, subranging (two-pass) A/D converter.
It processes signals at speeds comparable to a full
flash converter by using a sub-ranging conversion
technique with multiple comparator blocks, each
containing a sample and hold amplifier.
The ADC-305 features CMOS low power dis-
Pin
1
2
3
4
5
6
7
8
9
10
11
12
sipation (60mW typical) and a wide 18MHz (–1dB)
input signal bandwidth.
The ADC-305-1 is packaged in 400 mil 24-pin DIP
and the ADC-305-3 in 300 mil 24-pin SOP.
Other features are CMOS compatible input logic,
3-state TTL compatible output logic, +5V single
power operation, self bias mode and low cost.
FUNCTION
DGND
REF. BOTTOM (VRB)
SELF BIAS 1 (VRBS)
AGND
AGND
ANALOG INPUT (VIN)
+AVS (+5V)
REFERENCE TOP (VRT)
SELF BIAS 2 (VRTS)
+AVS (+5V)
+AVS (+5V)
+DVS (+5V)
FEATURES
INPUT/OUTPUT CONNECTIONS
FUNCTION
Pin
OUTPUT ENABLE (OE)
24
DGND
BIT 8 (LSB)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1 (MSB)
+DVS (+5V)
CLOCK INPUT (A/D CLK)
23
22
21
20
19
18
17
16
15
14
13
8-bit resolution, 20MHz min. sampling rate
±�½LSB max. differential nonlinearity error
18MHz input signal bandwidth
Subranging, S&H enclosed
+5V single power, low 85mW max. dissipation
CMOS compatible logic input
3-State TTL compatible output
Both the ADC-305-1 and the ADC-305-3 have the same pin assignment.
OUTPUT ENABLE 1
DGND 2
BIT 8 (LSB) 3
BIT 7 4
BIT 6 5
BIT 5 6
BIT 4 7
BIT 3 8
BIT 2 9
BIT 1 (MSB) 10
+DV
S
11
A/D CLK 12
CLOCK
GENERATOR
UPPER
DATA
LATCHES
LOWER
ENCODER
(4 BIT)
A BLOCK
COMPARATORS
WITH S/H (4 BIT)
LOWER
DATA
LATCHES
LOWER
ENCODER
(4 BIT)
B BLOCK
COMPARATORS
WITH S/H (4 BIT)
REFERENCE
VOLTAGE
24 DGND
23 V
RB
22 V
RBS
21 AGND
20 AGND
19 V
IN
18 +AV
S
17 V
RT
UPPER
ENCODER
(4 BIT)
UPPER
COMPARATORS
WITH S/H (4 BIT)
16 V
RTS
15 +AV
S
14 +AV
S
13 +DV
S
 
Figure 1. Functional Block Diagram
For full details go to
www.murata-ps.com/rohs
www.murata-ps.com
Technical enquiries
email: data.acquisition@murata-ps.com, tel:
+1 508 339 3000
MDA_ADC-305.B01
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