Register Bit Assignments
LANCAM A/L series (not recommended for new designs)
REGISTER BIT ASSIGNMENTS
Control Register Bits
Device
Bit(s)
15
14:13
Name
RST
Match Flag
Description
0 = Reset
00 = Enable
01 = Disable
10 = Reserved
11 = No Change
00 = Enable
01 = Disable
10 = Reserved
11 = No Change
00 = Input Not Translated
01 = Input Translated
10 = Reserved
11 = No Change
000 = 64 CAM/0 RAM
001 = 48 CAM/16 RAM
010 = 32 CAM/32 RAM
011 = 16 CAM/48 RAM
100 = 48 RAM/16 CAM
101 = 32 RAM/32 CAM
110 = 16 RAM/48 CAM
111 = No Change
00 = None
01 = MR1
10 = MR2
11 = No Change
00 = Increment
01 = Decrement
10 = Disable
11 = No Change
00 = Standard
01 = Enhanced
10 = Reserved
11 = No Change
12:11
Full Flag
10:9
Translation
8:6
CAM/RAM Part
All
5:4
Comp. Mask
3:2
AR Inc/Dec
1:0
Mode
Note:
D15 reads back as 0.
Segment Control Register Bits
Device
Bit(s)
15
14:13
12:11
10
9:8
7:6
5
4:3
2
1:0
Name
SDL
DCSL
DCEL
SSL
SCSL
SCEL
LDC
DSCV
LSC
SSCV
Description
0 = Set Destination Segment Limits
1 = No Change
00–11 = Destination Count Start Limit
00–11 = Destination Count End Limit
0 = Set Source Segment Limits
1 = No Change
00–11 = Source Count Start Limit
00–11 = Source Count End Limit
0 = Load Destination Segment Count
1 = No Change
00–11 = Destination Seg. Count Value
0 = Load Source Segment Count
1 = No Change
00–11 = Source Segment Count Value
All
Note:
D15, D10, D5, and D2 are read back as 0s.
Rev. 1
23
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