LANCAM A/L series (not recommended for new designs)
Operational Characteristics
Table 4: Standard and Enhanced Mode Device Select Response
Standard Mode
Case
1
2
3
4
5
6
2
Case
1
2
3
4
5
6
2
Internal
/EC(int)
1
1
1
0
0
0
Internal
/EC(int)
1
1
1
0
0
0
Internal
/MA(int)
X
X
X
X
1
0
Internal
/MA(int)
X
X
X
0
1
0
External
/MI
X
X
X
0
1
1
External
/MI
X
X
X
0
X
1
Device Select
Register
DS = FFFFH
DS = PA
DS
≠
FFFFH and
DS
≠
PA
X
X
X
Enhanced Mode
Device Select
Register
DS = FFFFH
DS = PA
DS
≠
FFFFH and
DS
≠
PA
X
X
X
Command
Write
1
YES
3
YES
3
NO
YES
3,6
YES
3,6
YES
3
Data
Write
YES
4
YES
4
NO
YES
3,7
YES
3,7
YES
4
Command
Read
NO
YES
NO
NO
5
NO
5
YES
5
Data
Read
NO
YES
NO
NO
NO
YES
Command
Write
1
YES
3
YES
3
NO
NO
NO
YES
3
Data
Write
YES
4
YES
4
NO
NO
NO
YES
4
Command
Read
NO
YES
NO
NO
5
NO
5
YES
5
Data
Read
NO
YES
NO
NO
NO
YES
Notes:
1.
Exceptions are:
A) A write to the Device Select register is always active in all devices;
B) A write to the Page Address register is active in the device with /FI LOW and /FF HIGH; and
C) The Set Full Flag (SFF) instruction is active in the device with /FI LOW and /FF HIGH.
If /MF is disabled in the Control register, Internal /MA is forced HIGH preventing a Case 6 response.
This is NO for a MOV instruction involving Memory at Next Free address if /FI is HIGH or the device is full.
This is NO if the Persistent Destination is Memory at Next Free address and /FI is HIGH or the device is full.
For a Command read following a TCO NF instruction, this is YES if the device contains the first empty location in a daisy chain (i.e., /FI LOW and
/FF HIGH) and NO if it does not.
This is NO for a MOV or VBC instruction involving Memory at Highest-Priority match.
This is NO if the Persistent Destination is Memory at Highest-Priority match.
2.
3.
4.
5.
6.
7.
Status Register
The 32-bit Status register, shown in Status Register Bits on
page 24, is the default source for Command Read cycles.
Bit 31 (internal Full flag) goes LOW if the particular
device has no empty memory locations. Bit 30 is the
internal Multiple Match flag, which goes LOW if a
Multiple match was detected. Bit 29 and Bit 28 are the
Validity bits, which reflect the validity of the last memory
location read. After a reset, the Validity bits read 11 until a
read or move from memory has occurred. The rest of the
Status register down to bit 1 contains the Page address of
the device and the address of the Highest-Priority match.
After a reset or a no-match condition, the match address
bits are all 1s. Bit 0 is the internal Match flag, which goes
LOW if a match was found in this particular device.
Comparand Register (CR)
The 64-bit Comparand register is the default destination
for data writes and reads, using the Segment Control
register to select which 16-bit segment of the Comparand
register is to be loaded or read out. The persistent source
and destination for data writes and reads can be changed to
the Mask registers or memory by SPS and SPD
instructions. During an automatic or forced compare, the
Comparand register is simultaneously compared against
the CAM portion of all memory locations with the correct
validity condition. Automatic compares always compare
against valid memory locations, while forced compares,
using CMP instructions, can compare against memory
locations tagged with any specific validity condition.
The Comparand register may be shifted one bit at a time to
the right or left by issuing a Shift Right or Shift Left
instruction, with the right and left limits for the
wrap-around determined by the CAM/RAM partitioning
12
Rev. 1
MUSIC [ MUSIC SEMICONDUCTORS ]
