WidePort LANCAM
®
Family
OPERATIONAL CHARACTERISTICS
Throughout the following, “aaaH” represents a three-
digit hexadecimal number “aaa,” while “bbB”
represents a two-digit binary number “bb.” All memory
locations are written to or read from in 32-bit segments.
Segment 0 corresponds to the lowest order bits (bits
31–0) and Segment 1 corresponds to the highest order
bits (bits 63–32).
Address register read where 0s will be read on DQ31–16
instead), as shown in Table 3.
The data and control interfaces to the WidePort LANCAM
are synchronous. During a Write cycle, the Control and
Data inputs are registered by the falling edge of /E. When
writing to the persistently selected data destination, the
Destination Segment counter is clocked by the rising edge
of /E. During a Read cycle, the Control inputs are registered
by the falling edge of /E, and the Data outputs are enabled
while /E is LOW. When reading from the persistently
selected data source, the Source Segment counter is clocked
by the rising edge of /E.
THE CONTROL BUS
Refer to the Block Diagram for the following discussion.
The inputs Chip Enable (/E), Write Enable (/W), Command
Enable (/CM), and Enable Daisy Chain (/EC) are the primary
control mechanism for the WidePort LANCAM. The /EC
input of the Control bus enables the /MF Match flag output
when LOW and controls the daisy chain operation.
Instructions are the secondary control mechanism. Logical
combinations of the Control Bus inputs, coupled with the
execution of Select Persistent Source (SPS), Select Persistent
Destination (SPD), and Temporary Command Override
(TCO) instructions allow the I/O operations to and from the
DQ31–0 lines to the internal resources, as shown in Table 4.
The Comparand register is the default source and destination
for Data Read and Write cycles. This default state can be
overridden independently by executing a Select Persistent
Source or Select Persistent Destination instruction, selecting
a different source or destination for data. Subsequent Data
Read or Data Write cycles will access that source or destination
until another SPS or SPD instruction is executed. The currently
selected persistent source or destination can be read back
through a TCO PS or PD instruction. The sources and
destinations available for persistent access are those resources
on the 64-bit bus: Comparand register, Mask Register 1, Mask
Register 2, and the Memory array.
The default destination for Command Write cycles is the
Instruction decoder, while the default source for Command
Read cycles is the Status register. The entire 32-bit Status
register is read in a single cycle.
Temporary Command Override (TCO) instructions provide
access to the Control register, the Page Address register,
the Segment Control register, the Address register, the Next
Free Address register, and Device Select register. These
instructions are only active for one Command Write cycle
to write a value into a register, or one Command Write cycle
followed by a Command Read cycle to read a register’s
contents. Each of these 16-bit registers is read out on the
DQ15–0 pins, with the upper 16 bits of the Status register
output on the DQ31–16 pins (except in the case of a Page
7
THE REGISTER SET
The Control, Segment Control, Address, Mask Register 1,
and the Persistent Source and Destination registers are
duplicated, with one set termed the Foreground set, and
the other the Background set. The active set is chosen by
issuing Select Foreground Registers or Select Background
Registers instructions. By default, the Foreground set is
active after a reset. Having two alternate sets of registers
that determine the device configuration allows for a rapid
return to a foreground network filtering task from a
background housekeeping task.
Writing a value to the Control register or writing data to the
last segment of the Comparand or either mask register will
cause an automatic comparison to occur between the
contents of the Comparand register and the words in the
CAM segments of the memory marked valid, masked by
MR1 or MR2 if selected in the Control register.
Instruction Decoder
The Instruction decoder is the write-only decode logic for
instructions and is the default destination for Command
Write cycles using the DQ31–16 lines. If the instruction
requires an absolute address or register value, the “f”
Address Field flag (bit 11) of the instruction is set to a “1,”
and the data on the DQ15–0 lines are written to the proper
register in that same cycle. If the instruction written is a
TCO, and the “f” bit is not set, the contents of the register
specified by the TCO may be read back by a successive
Command Read cycle to the DQ15–0 signal lines.
If the Address Field flag is set in a memory access
instruction, the absolute address supplied on the DQ15–0
lines is loaded into the Address register, and the instruction
completes at the new address. If the Address Field flag is not
set, the memory access occurs at the address currently
Rev. 2
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