Instruction Set Descriptions
LIST-XL Family
INSTRUCTION SET DESCRIPTIONS
Instruction: Select Persistent Source (SPS)
Binary Op-Code: 0000 f000 0000 0sss
f
Address Field flag
sss
Selected source
This instruction selects a persistent source for data reads, until
another SPS instruction changes it or a reset occurs. The
default source after reset for Data Read cycles is the
Comparand register. Setting the persistent source to M@aaaH
loads the Address register with "aaaH" and the first access to
that persistent source will be at aaaH, after which the AR value
increments or decrements as set in the Control register.The
SPS M@[AR]instruction does the same except the current
Address Register value is used.
Instruction: Temporary Command Override (TCO)
Binary Op-Code: 0000 0010 00dd d000
Register selected as source or
destination for only the next
Command Read or Write cycle
TCO instruction selects a register as the source or destination
for only the next Command Read or Write cycle, so a value
can be loaded or read out of the register. Subsequent Command
Read or Write Cycles revert to reading the Status register and
writing to the Instruction decoder.All registers but the NF, PS,
and PD can be written to, and all can be read from. The Status
register is only available via non-TCO Command Read
cycles. Reading the PS register also outputs the Device ID on
bits 15-4 as shown in Table 11 on page 16.
Instruction: Data Move (MOV)
Binary Op-Code: 0000 f011 mmdd dsss or
0000 f011 mmdd dvss
Address Field flag
Mask Register select
Destination of data
Source of data
Validity setting if destination is a
Memory location
The MOV instruction performs a 64-bit move of the data in
the selected source to the selected destination. If the source
or destination is aaaH, the Address register is set to "aaaH."
For MOV instructions to or from aaaH or [AR], the Address
register will increment or decrement from that value after the
move completes, as set in the Control register. Data transfers
between the Memory array and the Comparand register may
be masked by either Mask Register 1 or Mask Register 2, in
which case, only those bits in the destination which
correspond to bits in the selected mask register set to 0 will
be changed. A Memory location used as a destination for a
MOV instruction may be set to Valid or left unchanged. If the
source and destination are the same register, no net change
occurs (a NOP).
f
mm
ddd
sss
v
ddd
Instruction: Select Persistent Destination (SPD)
Binary Op-Code: 0000 f001 mmdd dvvv
Address Field flag
Mask Register select
Selected destination
Validity setting for Memory Location
destinations
This instruction selects a persistent destination for data writes,
which remains until another SPD instruction changes it or a
reset occurs. The default destination for Data Write cycles is
the Comparand register after a reset. When the destination is
the Comparand register or the memory array, the data written
may be masked by either Mask Register 1 or Mask Register
2, so that only destination bits corresponding to bits in the mask
register set to 0 will be modified. An automatic compare will
occur after writing the last segment of the Comparand or mask
registers, but not after writing to memory. Setting the
persistent destination to M@aaaH loads the Address register
with "aaaH," and the first access to that persistent destination
will be at aaaH, after which the AR value increments or
decrements as set in the Control register. The SPD M@[AR]
instruction does the same except the current Address Register
value is used.
f
mm
ddd
vvv
Rev. 3.1
11
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