LIST-XL Family
Register Bit Assignments
REGISTER BIT ASSIGNMENTS
Device
Bit(s)
15
Name
Description
0 = Reset
Reserved
RST
14:9
8:6
0
CAM/RAM Part
000 = 64 CAM/0 RAM
001 = 48 CAM/16 RAM
010 = 32 CAM/32 RAM
011 = 16 CAM/48 RAM
100 = 48 RAM/16 CAM
101 = 32 RAM/32 CAM
110 = 16 RAM/48 CAM
111 = No Change
All
5:4
3:2
1:0
Comp. Mask
AR Inc/Dec
0
00 = None
01 = MR1
10 = MR2
11 = No Change
00 = Increment
01 = Decrement
10 = Disable
11 = No Change
Reserved
Table 7: Control Register Bits
Note: D15 reads back as 0
Device
Bit(s)
Name
Description
15
SDL
0 = Set Destination Segment Limits
1 = No Change
14:13
12:11
10
DCSL
DCEL
SSL
00–11 = Destination Count Start Limit
00–11 = Destination Count End Limit
0 = Set Source Segment Limits
1 = No Change
9:8
7:6
5
SCSL
SCEL
LDC
00–11 = Source Count Start Limit
00–11 = Source Count End Limit
All
0 = Load Destination Segment Count
1 = No Change
4:3
2
DSCV
LSC
00–11 = Destination Seg. Count Value
0 = Load Source Segment Count
1 = No Change
1:0
SSCV
00–11 = Source Segment Count Value
Table 8: Segment Control Register Bits
Note: D15, D10, D5, and D2 are read back as 0s.
Device
Bit(s)
15:8
7:0
Name
Description
All 0’s
Reserved
NF7-0
3640L(F)
Next Free Address
All 0’s
15:9
8:0
Reserved
NF8-0
5640L(F)
Next Free Address
Table 9: Next Free Address Bits
Note: The Next Free Address register is read only, and is accessed by performing a Command Read cycle immediately following a TCO
NF Instruction.
16
Rev. 3.1
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