Operational Characteristics
LIST-XL Family
Mask Registers
There are two active mask registers at any one time, which
can be selected to mask comparisons or data writes. Mask
Register 1 has both a foreground and background mode to
support rapid context switching. Mask Register 2 does not
have this mode, but can be shifted left or right one bit at a time.
For masking comparisons, data stored in the active selected
mask register determines which bits of the comparand are
compared against the valid contents of the memory. If a bit
is set HIGH in the mask register, the same bit position in the
Comparand register becomes a "don't care" for the purpose
of the comparison with all the memory locations. During a
Data Write cycle or a MOV instruction, data in the specified
active mask register can also determine which bits in the
destination will be updated. If a bit is HIGH in the mask
register, the corresponding bit of the destination is unchanged.
Highest Priority/Multiple Match
The match line associated with each memory address is fed
into a priority encoder where multiple responses are resolved,
and the address of the highest-priority responder (the lowest
numerical match address) is generated. In LAN applications,
a multiple response might indicate an error. In other
applications the existence of multiple responders may be
valid.
Input Control Signals and Commands
Three input control signals and commands loaded into an
instruction decoder control the LIST-XL. Two of the three
input control signals determine the cycle type. The control
signals tell the device whether the data on the I/O bus
represents data or a command, and is input or output.
Commands are decoded by instruction logic and control
moves, forced compares, validity bit manipulations, and the
data path within the device. Registers (Control, Segment
Control, Address, Next Free Address, etc.) are accessed using
Temporary Command Override instructions. The data path
from the DQ bus to/from data resources (comparand, masks,
and memory) within the device are set until changed by Select
Persistent Source and Destination instructions.
After a Compare cycle (caused by either a data write to the
Comparand or mask registers, a write to the Control register,
or a forced compare), the Status register contains the address
of the Highest-Priority Matching location, along with flags
indicating match, multiple match, and full. The /MF, /MM,
and /FF flags also are available directly on output pins.
OPERATIONAL CHARACTERISTICS
Note:
Throughout the following, “aaaH” represents a three-digit hexadecimal number “aaa,” while “bbB” represents a two-digit
binary number “bb.” All memory locations are written to or read from in 16-bit segments. Segment 0 corresponds to the lowest order
bits (bits 15–0) and Segment 3 corresponds to the highest order bits (bits 63–48).
Control Bus
Refer to the Block Diagram on page 1 for the following
discussion. The inputs Chip Enable (/E), Write Enable (/W),
and Command Enable (/CM) are the primary control
mechanism for the LIST-XL. Instructions are the secondary
control mechanism. Logical combinations of the Control Bus
inputs, coupled with the execution of Select Persistent Source
(SPS), Select Persistent Destination (SPD), and Temporary
Command Override (TCO) instructions allow the I/O
operations to and from the DQ15-0 lines to the internal
resources, as shown in Table 3 on page 7.
The Comparand register is the default source and destination
for Data Read and Write cycles. This default state can be
overridden independently by executing a Select Persistent
Source or Select Persistent Destination instruction, selecting
a different source or destination for data. Subsequent Data
Read or Data Write cycles will access that source or
destination until another SPS or SPD instruction is executed.
The currently selected persistent source or destination can be
read back through a TCO PS or PD instruction. The sources
and destinations available for persistent access are those
Rev. 3.1
resources on the 64-bit bus: Comparand register, Mask
Register 1, Mask Register 2, and the Memory array.
The default destination for Command Write cycles is the
Instruction decoder, while the default source for Command
Read cycles is the Status register.
Temporary Command Override (TCO) instructions provide
access to the Control register, the Segment Control register,
the Address register, and the Next Free Address register. TCO
instructions are active only for one Command Read or Write
cycle after being loaded into the Instruction decoder.
The data and control interfaces to the LIST-XL are
synchronous. During a Write cycle, the Control and Data
inputs are registered by the falling edge of /E. When writing
to the persistently selected data destination, the Destination
Segment counter is clocked by the rising edge of /E. During
a Read cycle, the Control inputs are registered by the falling
edge of /E, and the Data outputs are enabled while /E is LOW.
When reading from the persistently selected data source, the
Source Segment counter is clocked by the rising edge of /E.
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MUSIC [ MUSIC SEMICONDUCTORS ]
