LIST-XL Family
Operational Characteristics
The Register Set
The Control, Segment Control, Address, Mask Register 1, and
the Persistent Source and Destination registers are duplicated,
with one set termed the Foreground set, and the other the
Background set. The active set is chosen by issuing Select
Foreground Registers or Select Background Registers
instructions. By default, the Foreground set is active after a
reset. Having two alternate sets of registers that determine the
device configuration allows for a rapid return to a foreground
network filtering task from a background housekeeping task.
Writing a value to the Control register or writing data to the
last segment of the Comparand or either mask register will
cause an automatic comparison to occur between the contents
of the Comparand register and the words in the CAM segments
of the memory marked valid, masked by MR1 or MR2 if
selected in the Control register.
Instruction Decoder
The Instruction decoder is the write-only decode logic for
instructions and is the default destination for Command Write
cycles. If an instruction's Address Field flag (bit 11) is set to
a 1, it is a two-cycle instruction that is not executed
immediately. For the next cycle only, the data from a
Command Write cycle is loaded into the Address register and
the instruction then completes at that address. The Address
register will then increment, decrement, or stay at the same
value depending on the setting of Control Register bits CT3
and CT2. If the Address Field flag is not set, the memory access
occurs at the address currently contained in the Address
register.
Control Register (CT)
The Control register is composed of a number of switches that
configure the LIST-XL, as shown in Table 7 on page
15. It is written or read using a TCO CT instruction. If bit 15
of the value written during a TCO CT is a 0, the device is reset
(and all other bits are ignored). See Table 4 for the Reset states.
Bit 15 always reads back as a 0. A write to the Control register
causes an automatic compare to occur (except in the case of
a reset). Either the Foreground or Background Control
register will be active, depending on which register set has
been selected, and only the active Control register will be
written to or read from.
Control Register bits 8-6 control the CAM/RAM partitioning.
The CAM portion of each word may be sized from a full 64
bits down to 16 bits in 16-bit increments. The RAM portion
can be at either end of the 64-bit word.
Compare masks may be selected by bits 5 and 4. Mask Register
1, Mask Register 2, or neither may be selected to mask
compare operations. The address register behavior is
controlled by bits 3 and 2, and may be set to increment,
decrement, or neither after a memory access.
6
Segment Control Register (SC)
The Segment Control register, as shown in Table 8 on page
16, is accessed using a TCO SC instruction. On read cycles,
D15, D10, D5, and D2 will always read back as 0s. Either the
Foreground or Background Segment Control register will be
active, depending on which register set has been selected, and
only the active Segment Control register will be written to or
read from.
The Segment Control register contains dual independent
incrementing counters with limits, one for data reads and one
for data writes. These counters control which 16-bit segment
of the 64-bit internal resource is accessed during a particular
data cycle on the 16-bit data bus. The actual destination for
data writes and source for data reads (called the persistent
destination and source) are set independently with SPD and
SPS instructions, respectively.
Each of the two counters consists of a start limit, an end limit,
and the current count value which points to the segment to be
accessed on the next data cycle. The current count value can
be set to any segment, even if it is outside the range set by the
start and end limits. The counters count up from the current
count value to the end limit and then jump back to the start
limit. If the current count is greater than the end limit, the
current count value will increment to 3, then roll over to 0 and
continue incrementing until the end limit is reached; it then
jumps back to the start limit.
If a sequence of data writes or reads is interrupted, the Segment
Control register can be reset to its initial start limit values by
using an RSC instruction. After the LIST-XL is reset, both
Source and Destination counters are set to count from
Segment 0 to Segment 3 with an initial value of 0.
Address Register (AR)
The Address register points to the CAM memory location to
be operated upon when M@[AR] or M@aaaH is part of the
instruction. It can be loaded directly by using a TCO AR
instruction or indirectly by using an instruction requiring an
absolute address, such as MOVaaaH, CR,V.After being
loaded, the Address register value will then be used for the
next memory access referencing the Address register. A reset
sets the Address register to zero.
Rev. 3.1
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