MU9C8148
PINOUT DIAGRAMS
60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41
NC
NC
NC
61
40
GND
D11
44
45
26
GND
62
63
39
38
D10
D9
D12
D13
25
24
DQ0
DQ1
64
65
37
36
A4
A3
46
47
D8
D7
D14
D15
23
22
DQ2
DQ3
A2
A1
66
67
35
34
48
49
D6
D5
/HBRDY
/HBEN
21
20
DQ4
DQ5
68
33
32
A0
/INT
50
51
D4
D3
69
70
/HBDIR
/RQ
MU9C8148
68-pin PLCC
MU9C8148
80-pin TQFP
19
18
DQ6
DQ7
/FULL,/EMPTY
/INTEL
31
30
71
72
73
52
53
/RQI
XFAIL,/FLUSH
D2
D1
29
28
/RESET
/EC
17
16
DQ8
DQ9
XMATCH
/RDY
54
55
D0
/WS, /UDS
/CM
/FI
74
75
27
26
15
14
DQ10
DQ11
RXD
RXC
56
57
/RS, /LDS
/CS
76
25
24
/MI
/E
13
12
DQ12
DQ13
77
78
VCC
NC
58
59
ALE, SRNW
/W
GND
VCC
23
22
79
80
11
10
DQ14
DQ15
NC
GND
GND
VCC
21
60
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20
PIN DESCRIPTIONS
(/X indicates an active LOW function)
LANCAM Interface:
/EC (Enable Comparison, Output, Three-state TTL)
The /EC signal enables the LANCAM /MF pin to output the
results of a comparison. If /EC is LOW at the falling edge of /E
for a given cycle, the LANCAM /MF output is enabled on the
rising edge of /E. If /EC is HIGH, the LANCAM /MF output is
held HIGH.
DQ15–DQ0 (Data Bus, Input/Output, TTL)
The DQ15–DQ0 lines transfer data, commands and status
between the MU9C8148 and the LANCAM. The direction and
nature of the information that flows between the devices is
determined by the states of /CM and /W.
/MI (Match Flag, Input, TTL)
/E (Chip Enable, Output, Three-state TTL)
The LANCAM /MF pin takes the MU9C8148's /MI input LOW if
a valid match occurs during a Comparison cycle, and /EC was
also LOW at the start of that cycle. The state of the /MI pin
controls branching in the MU9C8148's routines.
The /E output enables the LANCAM while LOW and registers
/W, /CM, /EC and DQ15–DQ0 (if /W is LOW) on the falling
edge of /E. If /W is HIGH, data on DQ15–DQ0 from the
LANCAM is valid on the rising edge of /E.
/FI (Full Flag, Input, TTL)
/W (Write Enable, Output, Three-state TTL)
The /FI input will be driven LOW by the LANCAM /FF output pin
if all the LANCAM memory locations have valid contents. The
status of the /FI pin can be read by the Host processor from the
MU9C8148's Control register.
The /W output selects the direction of data flow during a
LANCAM cycle. DQ15–DQ0 write to the LANCAM if /W is LOW
at the falling edge of /E. Read data is output from the LANCAM
to DQ15–DQ0 on the rising edge of /E if /W is HIGH at the
falling edge of /E.
Transceiver Interface:
RXD
(Receive Data, Input, TTL)
/CM (Data/Command Select, Output, Three-state
TTL)
The RXD pin monitors the data received by the TMS38053/4
from the Token Ring. RXD is clocked on the rising edge of
RXC.
The /CM signal determines whether DQ15–DQ0 contain
LANCAM data or commands. /CM is LOW at the falling edge
of /E for Command cycles and HIGH for Data cycles.
Rev. 5.5 Draft web
2
MUSIC [ MUSIC SEMICONDUCTORS ]
