Pin Descriptions
INCR (Increment Time Stamp Counters, Input, TTL)
MU9C8338A 10/100Mb Ethernet Filter Interface
/WRITE (Processor Port Read/Write, Input, TTL)
INCR is a user command to invoke the built-in purge
routine. Both STCURR and STPURG 8-bit counters are
advanced one count on the rising edge of INCR, and the
time stamp stored with each LANCAM entry is compared
with STPURG. Matching entries subsequently are purged
or deleted. This pin must be configured, if it is required, by
setting bit 2 and bit 3 in the System Target (STARG)
register. INCR must be held HIGH for a minimum of one
SYSCLK cycle. Consecutive assertions of INCR must be
a minimum of 8 SYSCLK cycles apart. Each counter can
be incremented individually through the Processor Port.
(see Operational Characteristics: STARG System Target
Register Mapping).
Read/Write determines the direction of data flow into or
out of the MU9C8338A host processor interface. If
/WRITE is LOW, the data is written into the register
selected by A[7:0] and /PCS or /PCSS; if HIGH, the data
is read from the register selected by A[7:0] and /PCS or
/PCSS.
A[7:0] (Processor Port Address, Input, TTL)
Processor Address bus A[7:0] selects the MU9C8338A
register accessed by the host processor.
D[15:0] (Processor Port Data, Input/Output, Tri-state,
TTL)
Host Processor Interface
The Host Processor interface is asynchronous to the
System Clock. This interface is controlled by the /PCS or
/PCSS (whichever is appropriate) and PROC_RDY
signals, which form the handshaking between the
processor and the MU9C8338A. This allows the end
system to use a processor that runs at a different clock
speed than the clock required by the MU9C8338A. (see
Timing Diagrams: Timing Data for Host Processor
Interface).
/PCS (Processor Port Chip Select, Input, TTL)
Processor Data bus D[15:0] is the tri-state processor data
bus for the MU9C8338A.
PROC_RDY (Processor Port Ready, Output, Tri-state,
TTL)
When reading from or writing to any MU9C8338A
internal register, the PROC_RDY tri-state output goes
LOW on the falling edge of /PCS or /PCSS. If it is a read
cycle, PROC_RDY goes HIGH on the rising edge of
SYSCLK once data is available. If it is a write cycle,
PROC_RDY goes HIGH on the rising edge of SYSCLK
when the internal register is ready to accept data.
/INTR (Processor Interrupt, Output, TTL)
Processor Chip Select is taken LOW by the host processor
to gain access to the MU9C8338A Port or Chip registers.
/PCSS (Processor Port Chip Select System, Input, TTL)
Processor Chip Select System is taken LOW by the host
processor to gain access to the MU9C8338A System
registers or to access the LANCAM.
/INTR goes LOW to signal that one of the two
configurable interrupt conditions have been satisfied. The
two separate conditions are configured by setting bits in
the appropriate register. /INTR returns HIGH when the
appropriate register is read. See Table 2 for details of
which interrupt conditions are possible and which register
must be read to reset the /INTR pin to HIGH.
Table 2: /INTR Settings
Register Required to To clear /INTR, Read
Select Interrupt
Condition
PTARG
Interrupt Condition
RSTAT. Please note that /INTR will only return
The MII port has parsed an incoming packet. The DA lookup
HIGH when all possible result data has been read. has been performed and the result data is available to be
read from RDAT register.
SSTAT. Please note that /INTR will only return
HIGH when the LANCAM has become not full.
Therefore, after the SSTAT register read has
confirmed the status of the interrupt condition, an
entry should be removed from the LANCAM by
using the PURGE sequence.
The /FF output from the LANCAM(s) has indicated that the
LANCAM is full. When reading the SSTAT register, a full
condition is indicated by bit 0 = 0.
STARG
Rev. 0a
5
MUSIC [ MUSIC SEMICONDUCTORS ]
