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All signals are implemented in CMOS technology with TTL levels. Signal names that start with a slash (“/”) are active
LOW. Inputs should never be left floating. Pins designated as "Reserved" must not be connected to any external circuitry.
Refer to the Electrical Characteristics section for more information.
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RXD[3:0] is the 4-bit MII Receive Data nibble (see
Timing Diagrams: Timing Data for RXD, RX_DV, and
RX_ER).
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Data Valid is on RX_DV; RX_DV is asserted by the PHY
at the beginning of the first nibble of the data frame and
deasserted at the end of the last nibble of the frame. It
indicates that the data is synchronous to RX_CLK and is
itself synchronous to the clock (see Timing Diagrams:
Timing Data for RXD, RX_DV, and RX_ER).
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RX_ER indicates a data symbol error in 100Mb/s mode or
any other error that the PHY can detect, even if the MAC
is not capable of detecting that error (see Timing
Diagrams: Timing Data for RXD, RX_DV, and RX_ER).
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RX_CLK is the receive clock recovered from the data by
the PHY. It is equal to 25 MHz in 100Base-X mode or 2.5
MHz in 10Base-X mode.
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Carrier sense CRS indicates that the medium is active
(non-idle) and remains asserted during a collision. For Rx
or Tx: CRS is HIGH in 10/100Base-X half-duplex mode;
for Rx it is HIGH in repeater, full-duplex, and loopback
modes. CRS is not synchronized to RX_CLK.
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Collision detect COL is asserted by the PHY upon
detection of a collision on the medium and remains
asserted as long as the collision persists. It is HIGH in
half-duplex modes and remains HIGH for 1 microsecond
following the end of transmission; it is LOW in
full-duplex mode. It is asserted in response to
signal_quality_error message from the PMA in 10Base-X
Heartbeat mode.
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REJ is the reject packet command issued by the
MU9C8358L; the minimum length is 110 nanoseconds.
REJ is driven HIGH to reject a data frame, and can be
detected by and responded to by the MAC devices from 2
bit times after SFD to 512 bit times (64 byte times) after
SFD. The REJ signal can be made active LOW by setting
Bit 0 in the SSCFG register. (See Timing Diagrams:
Timing Data for REJ (Base 100.))
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The Forced Receive Error pins provide the logical OR of
the RX_ER and REJ lines for the appropriate MII port (see
Timing Diagrams: Timing Data for FRX_ER in Relation
to REJ and RX_ER).
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The Tag Port Serial Data pin carries the destination Port
ID to external circuitry as soon as it is collected from the
CAM (see Timing Diagrams: Timing Data for Tag Ports
TP_DV and TP_SD).
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The Tag Port Data Valid pins are driven HIGH for as long
as unread data exists for each Destination Port ID. Pins
TP_SD_A through TP_SD_D carry the Destination Port
ID (4 bits) to external circuitry as soon as it is collected
from the CAM (see Timing Diagrams: Timing Data for
Tag Ports TP_DV and TP_SD).
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