MUAA Routing CoProcessor (RCP) Family
Pin Descriptions
/DOUTVALID (Output)
/DOUTVALID indicates when new data is available at the
synchronous output port. /DOUTVALID is active LOW
for one CLK cycle. /DOUTVALID may be configured to
become active on the same clock as new DOUT becomes
valid or the CLK before. The JTAG interface is able to set
/DOUTVALID to HIGH-Z.
/OE (Input)
/OE is the DOUT High Impedance control.
/DOUTE (Input)
/DOUTE is the DOUT enable control. When the DOUT
data word is configured to be wider than the output port
then this strobe enables the next word(s) of the DOUT data
onto the DOUT pins.
PROCD[31:0] (Bi-directional)
The bi-directional Processor data port provides the
processor interface to the device. On write cycles all
devices respond in parallel. On read cycles the appropriate
device responds without additional intervention from the
processor.
PROCA[5:0] (Input)
Processor port address bus. Selects which device register
is accessed. Bit 0 is only used when the port is set to 16-bit
mode, otherwise it should be held at a valid logic level.
R/W (Input)
R/W is the processor port read/write control pin. This pin
is HIGH for reads, LOW for writes.
/PCS (Input)
/PCS is the processor port chip select pin. When LOW this
pin indicates a cycle to the processor port. On write cycles
data must be set up to the rising edge of /PCS. On read
cycles /PCS controls the output enable of the PROCD bus.
Note that /PCS may be asynchronous to CLK. Refer to
PROCREADY (Output)
When PROCREADY is HIGH, indicates the processor
read data is available or the processor write data is
accepted. Priority may be set between the DIN port and
the processor port. Note PROCREADY may be LOW for
up to 800 CLK periods after /RESET is taken HIGH. The
JTAG interface is able to set PROCREADY to HIGH-Z.
INT (Output)
INT interrupt. Indicates the aged or learned queue has at
least one entry or a write exception occurred. The service
routine should either check the AQUEUE, LQUEUE, and
WEX registers, or bits 26–29 of the Address Index
register, to determine the cause. The interrupt is cleared
after the appropriate flag register has been read and will
not be reasserted until either the queue(s) are emptied and
4
then get at least one entry again, or another write
exception occurs. The JTAG interface is able to set INT to
HIGH-Z.
/RESET (Input)
The /RESET input is used to reset the MUAA RCP.
/RESET must be asserted for at least 3 CLK periods.
CLK (Input)
The rising edge of CLK input is the device clock.
/FF (Full Flag, Output)
/FF is active when the device (or chain of devices) is full.
/FF becomes inactive when any one device has two open
entries. The JTAG interface is able to set /FF to HIGH-Z.
CHAIN[3:0 (Input)
When two or more devices are chained they communicate
among themselves using the CHAIN[3:0] signals. See
Chaining section. Internally Pulled-up. Refer to Table 1
for slave connections.
CHAINUP (Output)
When two or more devices are chained they communicate
among themselves using the CHAINUP signals. See
Chaining section. The JTAG interface is able to set
CHAINUP to HIGH-Z. Refer to Table 1 for slave
connections.
CHAINDN (Output)
When two or more devices are chained they communicate
among themselves using the CHAINDN signals. See
Chaining section. The JTAG interface is able to set
CHAINDOWN to HIGH-Z. Refer to Table 1 for slave
connections.
CHAINCS (Bi-directional)
When two or more devices are chained they communicate
among themselves using the CHAINCS signals. See
Chaining section. Internally pulled up. Refer to Table 1 for
slave connections.
/MF (Match Flag, Output)
The /MF output indicates whether a match was found. The
JTAG interface is able to set /MF to HIGH-Z.
/TRST (JTAG Reset, Input)
The /TRST is the Test Reset pin. Internally pulled up with
25K minimum. Must be tied to /RESET or tied LOW
when not in use.
/TCLK (JTAG Test Clock, Input)
The /TCLK input is the Test Clock input. Must be tied at a
valid logic level when not in use.
TMS (JTAG Test Mode Select, Input)
The TMS input is the Test Mode Select input. Internally
pulled up with 25K minimum.
Rev. 5
MUSIC [ MUSIC SEMICONDUCTORS ]
