N64T1618CBB
Advance Information
NanoAmp Solutions, Inc.
Table 1. Ball Description
SYMBOL
TYPE
DESCRIPTION
A0-A21
Input
Address Inputs: Inputs for addresses during READ and WRITE operations.
Addresses are internally latched during READ and WRITE cycles. The address
lines are also used to define the value to be loaded into the Bus Configuration
Register or the Refresh Configuration Register.
CLK
Input
Input
Clock: Synchronizes the memory to the system operating frequency during syn-
chronous operations. When configured for synchronous operation, the address is
latched on the first rising (or falling, depending upon the Bus Configuration Regis-
ter setting) CLK edge when ADV# is active, or upon a rising ADV# edge, which-
ever occurs first. CLK is static during asynchronous access READ and WRITE
operations and during PAGE READ ACCESS operations.
Address Valid: Indicates that a valid address is present on the address inputs.
Addresses can be latched on the rising edge of ADV# during READ and WRITE
operations. ADV# may be driven LOW during asynchronous READ and WRITE
operations.
ADV#
CRE
CE#
OE#
WE#
Input
Input
Input
Input
Control Register Enable: When CRE is HIGH, write operations load the Refresh
Control Register or Bus Control Register.
Chip Enable: Activates the device when LOW. When CE# is HIGH, the device is
disabled and goes into standby power mode.
Output Enable: Enables the output buffers when LOW. When OE# is HIGH, the
output buffers are disabled.
Write Enable: Determines if a given cycle is a WRITE cycle. If WE# is LOW, the
cycle is a WRITE to either a control register or to the memory array.
UB#
LB#
Input
Input
Upper Byte Enable. I/O <8:15>
Lower Byte Enable. I/O <0:7>
I/O0-I/O15 Input/Out- Data Inputs/Outputs
put
WAIT
Output
Wait: Provides data-valid feedback during burst READ and WRITE operations.
The signal is gated by CE#. WAIT is used to arbitrate collisions between refresh
and READ/WRITE operations. WAIT is asserted when a burst crosses a row
boundary. WAIT is also used to mask the delay associated with opening a new
internal page. WAIT is asserted and should be ignored during asynchronous and
page mode operations. WAIT is high-Z when CE# is high.
NC
–
Internally not connected
Vcc
VccQ
Vss
Supply
Supply
Supply
Supply
Device Power Supply: [1.70V-1.95V] Power supply for device core operation.
I/O Power Supply: [1.8V, 2.5V, 3.0V]Power supply for input/output buffers.
All Vss supply pins must be connected to ground.
VssQ
All VssQ supply pins must be connected to ground.
NOTE: The CLK and ADV# inputs can be tied to VSS if the device is always operating in asynchronous or page mode. The WAIT sig-
nal will be driven to an undefined state when operating in asynchronous or page mode.
Stock No. 23310-H 1/05
This is an ADVANCE DATASHEET and subject to change without notice.
3
NANOAMP [ NANOAMP SOLUTIONS, INC. ]
