NanoAmp Solutions, Inc.
Functional Description
NT5DS64M4CT, NT5DS32M8CT, NT5DS16M16CT
NT5DS64M4CS, NT5DS32M8CS, NT5DS16M16CS
The 256Mb DDR SDRAM is a high-speed CMOS, dynamic random-access memory containing 268, 435, 456 bits. The 256Mb
DDR SDRAM is internally configured as a quad-bank DRAM.
The 256Mb DDR SDRAM uses a double-data-rate architecture to achieve high-speed operation. The double-data-rate architec-
ture is essentially a
2n
prefetch architecture, with an interface designed to transfer two data words per clock cycle at the I/O
pins. A single read or write access for the 256Mb DDR SDRAM consists of a single
2n-bit
wide, one clock cycle data transfer at
the internal DRAM core and two corresponding n-bit wide, one-half clock cycle data transfers at the I/O pins.
Read and write accesses to the DDR SDRAM are burst oriented; accesses start at a selected location and continue for a pro-
grammed number of locations in a programmed sequence. Accesses begin with the registration of an Active command, which is
then followed by a Read or Write command. The address bits registered coincident with the Active command are used to select
the bank and row to be accessed (BA0, BA1 select the bank; A0-A12 select the row). The address bits registered coincident
with the Read or Write command are used to select the starting column location for the burst access.
Prior to normal operation, the DDR SDRAM must be initialized. The following sections provide detailed information covering
device initialization, register definition, command descriptions and device operation.
Initialization
Only one of the following two conditions must be met.
• No power sequencing is specified during power up or power down given the following criteria:
V
DD
and V
DDQ
are driven from a single power converter output
V
TT
meets the specification
A minimum resistance of 42 ohms limits the input current from the VTT supply into any pin and
V
REF
tracks V
DDQ
/2
or
• The following relationships must be followed:
V
DDQ
is driven after or with V
DD
such that V
DDQ
< V
DD
+ 0.3V
V
TT
is driven after or with V
DDQ
such that V
TT
< V
DDQ
+ 0.3V
V
REF
is driven after or with V
DDQ
such that V
REF
< V
DDQ
+ 0.3V
The DQ and DQS outputs are in the High-Z state, where they remain until driven in normal operation (by a read access). After
all power supply and reference voltages are stable, and the clock is stable, the DDR SDRAM requires a 200µs delay prior to
applying an executable command.
Once the 200µs delay has been satisfied, a Deselect or NOP command should be applied, and CKE must be brought HIGH.
Following the NOP command, a Precharge ALL command must be applied. Next a Mode Register Set command must be
issued for the Extended Mode Register, to enable the DLL, then a Mode Register Set command must be issued for the Mode
Register, to reset the DLL, and to program the operating parameters. 200 clock cycles are required between the DLL reset and
any read command. A Precharge ALL command should be applied, placing the device in the “all banks idle” state
Once in the idle state, two auto refresh cycles must be performed. Additionally, a Mode Register Set command for the Mode
Register, with the reset DLL bit deactivated (i.e. to program operating parameters without resetting the DLL) must be performed.
Following these cycles, the DDR SDRAM is ready for normal operation.
DDR SDRAM’s may be reinitialized at any time during normal operation by asserting a valid MRS command to either the base
or extended mode registers without affecting the contents of the memory array. The contents of either the mode register or
extended mode register can be modified at any valid time during device operation without affecting the state of the internal
address refresh counters used for device refresh.
DOC # 14-02-044 Rev A ECN # 01-1116
The specifications of this device are subject to change without notice. For latest documentation, see http://www.nanoamp.com
8
NANOAMP [ NANOAMP SOLUTIONS, INC. ]
