DATA SHEET
DATA SHEET
CMOS DIGITAL INTEGRATED CIRCUITS
P
PD2845GR
1 V, 1.3 mA, 94MHz PLL SYNTHESIZER LSI
FOR PAGER SYSTEM
DESCRIPTION
P
PD2845GR is a PLL synthesizer LSI for pager system. This LSI is manufactured using low voltage CMOS
process and therefore realized the low power consumption PLL operated on 1 V, 1.3 mA. This LSI is packaged in 16
pin plastic SSOP suitable for high-density surface mounting. So, this product contributes to produce a long-life-
battery and physically-small pager system.
FEATURES
• Operating frequency : · Input frequency : f
in
= 10 MHz to 94 MHz
· Reference oscillating frequency : f
x’tal
= 12.8 MHz
• Low Supply voltage : · PLL block : V
DD1
= 1.00 V to 1.15 V @ f
in
= 10 MHz to 70 MHz
V
DD1
= 1.05 V to 1.15 V @ f
in
= 10 MHz to 94 MHz
· Charge pump block: V
DD2
= 3.0 V ± 300 mV
• Low power consumption
•
I
DD
= 1.3 mA TYP. @ f
in
= 70 MHz, f
x’tal
= 12.8 MHz
• Equipped with power-save function
•
Serial data can be received in power-save mode.
• Packaged in 16 pin plastic SSOP suitable for high-density surface mounting.
ORDERING INFORMATION
PART NUMBER
PACKAGE
16 pin plastic SSOP
(225 mil)
16 pin plastic SSOP
(225 mil)
SUPPLYING FORM
Embossed tape 12 mm wide. QTY 2.5 k/reel
Pin 1 is in tape pull-out direction.
Embossed tape 12 mm wide. QTY 2.5 k/reel
Pin 1 is in tape roll-in direction.
P
PD2845GR-E1
P
PD2845GR-E2
* To order evaluation samples, please contact your local NEC sales office (Order number :
P
PD2845GR).
PIN ASSIGNMENT
(Top View)
V
DD1
F
IN
GND
FR
RESET
EO
EOP
EON
XI
XO
LE
CLK
DATA
PS
NC
V
DD2
Caution Electro-static sensitive devices
Document No. P12150EJ2V0DS00 (2nd edition)
(Previous No. IC-3291)
Date Published February 1997 N
Pi di J
©
1994
NEC [ NEC ]
