µ
PD31172
1. PIN FUNCTIONS
1.1
Pin Function List
(1) System bus interface signals
Signal Name
SCLK
AD (0:24)
DATA (0:31)
LCDCS#
RD#
I/O
I/O
I/O
I/O
Input
I/O
This is the SDRAM operating clock.
These form a 25-bit address bus.
These form a 32-bit data bus.
This is the LCD chip select signal. This signal becomes active when the V
R
4121 accesses the
LCD using the AD or data bus.
•
Output: This signal becomes active when the V
RC
4172 accesses SDRAM.
•
Input:
WR#
I/O
This signal becomes active when the V
R
4121 reads data from the V
RC
4172’s PCI
host bridge.
Function
•
Output: This signal becomes active when the V
RC
4172 writes data to SDRAM.
•
Input:
This signal becomes active when the V
R
4121 writes data to the V
RC
4172’s PCI host
bridge.
LCDRDY
ROMCS (2:3)#
CKE
UUCAS#
ULCAS#
MRAS (0:1)#
UCAS#
LCAS#
IOR#
IOW#
RESET
IOCS16#
IOCHRDY
HOLDRQ#
HOLDAK#
SRAS#
SCAS#
BUSRQ (0:1)#
BUSAK (0:1)#
INTRP
IRQ
USBINT#
PS2INT
BUSCLK
ARBCLKSEL
Output
I/O
I/O
I/O
I/O
I/O
I/O
I/O
Input
Input
Input
Output
Output
Output
Input
I/O
I/O
Input
Output
Output
Output
Output
Output
Input
Input
This is the LCD ready signal. This signal becomes active when a state is entered whereby the
V
RC
4172 can acknowledge an access to the LCD area from the V
R
4121.
This is an SDRAM chip select signal.
This is the SDRAM clock enable signal.
This is an SDRAM DQM signal. This signal controls the I/O buffers for the DATA (24:31) pins.
This is an SDRAM DQM signal. This signal controls the I/O buffers for the DATA (16:23) pins.
This is an SDRAM chip select signal.
This is an SDRAM DQM signal. This signal controls the I/O buffers for the DATA (8:15) pins.
This is an SDRAM DQM signal. This signal controls the I/O buffers for the DATA (0:7) pins.
This is the system bus I/O read signal. This signal becomes active when any resource except
the USB inside the V
RC
4172 is accessed.
This is the system bus I/O write signal. This signal becomes active when
any
resource except
the USB inside the V
RC
4172 is accessed.
This is the system bus reset signal.
This is the dynamic bus-sizing request signal.
This is the system bus ready signal.
This is the system bus access right request signal.
This is the system bus access enable signal.
This is the SDRAM RAS signal.
This is the SDRAM CAS signal.
This is a signal input from the external bus master requesting access to the system bus.
This is a signal output to the external bus master permitting access to the system bus.
This is an interrupt request signal from the 16550 serial controller or the IEEE1284 parallel
controller.
This is an interrupt request signal from the general-purpose ports (GPIO (0:23)) or the
IEEE1284 parallel controller.
This is an interrupt request signal from the USB host controller.
This is an interrupt request signal from the PS/2 controller.
This is the system bus clock.
This is a clock select signal for arbitrating the system bus (controls the HOLDRQ# signal)
(1: Internal clock used, 0: BUSCLK used)
8
Data Sheet U14388EJ2V0DS00
NEC [ NEC ]
