DATA SHEET
MOS INTEGRATED CIRCUIT
µ
PD485506
LINE BUFFER
5K-WORD BY 16-BIT/10K-WORD BY 8-BIT
Description
The
µ
PD485506 is a high speed FIFO (First In First Out) line buffer. Word organization can be changed either
5,048 words by 16 bits or 10,096 words by 8 bits. Its CMOS static circuitry provides high speed access and low power
consumption.
The
µ
PD485506 can be used for one line delay and time axis conversion in high speed facsimile machines and
digital copiers.
Moreover, the
µ
PD485506 can execute read and write operations independently on an asynchronous basis. Thus
the
µ
PD485506 is suitable as a buffer for data transfer between units with different transfer rates and as a buffer for
the synchronization of multiple input signals.
There are four versions, E, K, P, X and L. This data sheet can be applied to the version X and L. These versions
operate with different specifications. Each version is identified with its lot number (refer to
7. Example of Stamping).
Features
• 5,048 words by 16 bits (Word mode) /10,096 words by 8 bits (Byte mode)
• Asynchronous read/write operations available
• Variable length delay bits; 21 to 5,048 bits or 10,096 bits (Cycle time: 25 ns)
15 to 5,048 bits or 10,096 bits (Cycle time: 35 ns)
• Power supply voltage V
CC
= 5.0 V
±0.5
V
• Suitable for sampling two lines of A3 size paper (16 dots/mm)
• All input/output TTL compatible
• 3-state output
• Full static operation; data hold time = infinity
Ordering Information
Part Number
R/W Cycle Time
25 ns
35 ns
Package
44-pin plastic TSOP (II) (10.16 mm (400))
µ
PD485506G5-25-7JF
µ
PD485506G5-35-7JF
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for availability
and additional information.
Document No. M10060EJ7V0DSJ1 (7th edition)
Date Published December 2000 N CP(K)
Printed in Japan
The mark
shows major revised points.
©
1994
NEC [ NEC ]
