SM5002L series
Load cct 1
Q output
C
L
(Including probe capacity)
C
L
= 15pF: t
r1
, t
f1
/DUTY, I
DD
(70MHz
<
f
≤
100MHz)
C
L
= 30pF: t
r2
, t
f2
/DUTY, I
DD
(f
≤
70MHz)
Switching Time Measurement Waveform
Output duty level (CMOS)
Q output
0.9V
DD
0.1V
DD
T
W
0.9V
DD
0.1V
DD
DUTY measuring
voltage (0.5V
DD
)
t
r
Output duty cycle (CMOS)
t
f
Q output
T
W
T
DUTY measuring
voltage
(
0.5V
DD
)
DUTY= T
W
/ T
100 (%)
Output Enable/Disable Delay
The following figure shows the oscillator timing during normal operation. Note that when the device is in
standby, the oscillator stops. When standby is released, the oscillator starts and stable oscillator output occurs
after a short delay.
INH
V
IL
V
IH
t
PLZ
Q output
INH inputwaveform
t
r =
t
f
t
PZL
10ns
NIPPON PRECISION CIRCUITS—8