SM588
×
series
BLOCK DIAGRAM
LRCI
DATA
Input interface
L
R
BCKI*
CLK
Timing
control
Filter & attenuation
operation block
L
R
DEEM**
Noise shaper
operation block
9 Level
DEM DAC
9 Level
DEM DAC
9 Level
DEM DAC
9 Level
DEM DAC
+
−
−
+
LO
* : Not available for 2-wire input type
** : Not available for 3-wire input type
VSS VDD
RO
PIN DESCRIPTION
Number
1
2
3
4
5
6
7
8
1.
2.
Name
DATA
BCKI
1
DEEM
2
LRCI
CLK
RO
VSS
VDD
LO
I/O
I
I
I
I
I
O
–
–
O
Serial data input
Bit clock input
Deemphasis ON/OFF control (44.1 kHz, ON when HIGH)
Sample rate (fs) clock input. Left-channel input when HIGH, and right-channel input when LOW.
External clock input
Right-channel analog output
Ground
Supply
Left-channel analog output
Description
3-wire type
2-wire type with built-in deemphasis filter
NIPPON PRECISION CIRCUITS—3
NPC [ NIPPON PRECISION CIRCUITS INC ]
