SM6451AV
BLOCK DIAGRAM
DVDD
DVSS
Attenuation
Control
1/2V
DD
MLEN
MCK
MDT
RSTN
Chip
Address
Decoder
ADRS1
ADRS2
VRL
Reference
Voltage
Circuits
Attenuation Decoder
Interface Control
LIN
LOUT
VRR
1/2V
DD
RIN
Attenuation
Control
AVDD
AVSS
ROUT
PIN DESCRIPTION
Number
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
1.
Name
RSTN
ADRS1
ADRS2
DVDD
LOUT
LIN
AVDD
VRL
VRR
AVSS
RIN
ROUT
DVSS
MLEN
MCK
MDT
I/O
1
Ip
Ip
Ip
–
O
I
–
O
O
–
I
O
–
Ip
Ip
Ip
A/D
1
D
D
D
D
A
A
A
A
A
A
A
A
D
D
D
D
Description
System reset input (LOW-level reset)
Chip address set 1
Chip address set 2
Digital supply
Left-channel audio output
Left-channel audio input
Analog supply
Left-channel reference voltage (0.5V
DD
). Connect a 10 µF capacitor
between VRL and AVSS.
Right-channel reference voltage (0.5V
DD
). Connect a 10 µF capacitor
between VRR and AVSS.
Analog ground
Right-channel audio input
Right-channel audio output
Digital ground
Microcontroller latch enable input
Microcontroller clock input
Microcontroller data input
Ip = input pin with pull-up, A = analog, D= digital
NIPPON PRECISION CIRCUITS—2
NPC [ NIPPON PRECISION CIRCUITS INC ]
