SM6802A
BLOCK DIAGRAM
LEQP
LEQN
TESTN DRCN PWDN MUTEN
VDD3
LIN
−
+
LEVEL SHIFTER
PWM
Modulator
LEVEL SHIFTER
BUFFER
LOUTP
−
+
BUFFER
LOUTN
VREF1
RIN
REQP
REQN
BIAS
VREF
−
+
OSC
MUTE,POWERDOWN,
PROTECTION
VSS2
LEVEL SHIFTER
PWM
Modulator
LEVEL SHIFTER
BUFFER
ROUTP
−
+
BUFFER
ROUT
VSS1 VDD1
VDD2
PIN DESCRIPTION
Number
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
Name
*1
LEQP
LIN
VDD1
RIN
REQP
REQN
VSS1
PDWN
DRCN
ROUTN
VDD2
ROUTP
VSS2
LOUTP
VDD3
LOUTN
MUTEN
TESTN
VREF1
LEQN
I/O
*2
I
I
–
I
I
I
–
I
I
O
–
O
–
O
–
O
I
Ip
–
O
Lch equalizer network connection
Lch signal input
Supply (input system)
Rch signal input
Rch equalizer network connection
Rch equalizer network connection
Ground (input system)
Power-down control (active LOW)
Dynamic range compression mode setting (HIGH: normal operation, LOW: compression mode)
Rch speaker minus (–) output
Supply (output stage)
Rch speaker plus (
+
) output
Ground (output stage)
Lch speaker plus (
+
) output
Supply (output stage)
Lch speaker minus (–) output
Mute control (active LOW)
Test pin (HIGH: normal operation, LOW: test mode)
Reference voltage 1 (bias voltage)
Lch equalizer network connection
Function
*1. V
DDS
= VDD1, V
DDP
= VDD2 = VDD3, V
SS
= VSS1 = VSS2
*2. Ip = input pin with built-in pull-up resistor
NIPPON PRECISION CIRCUITS INC.—2
NPC [ NIPPON PRECISION CIRCUITS INC ]
