August 1998
100315
Low-Skew Quad Clock Driver
n Differential inputs and outputs
n Secondary clock available for system level testing
n 2000V ESD protection
n Voltage compensated operating range: −4.2V to −5.7V
n Standard Microcircuit Drawing
(SMD) 5962-9469601
General Description
The 100315 contains four low skew differential drivers, de-
signed for generation of multiple, minimum skew differential
clocks from a single differential input. This device also has
the capability to select
a secondary single-ended clock
source for use in lower frequency system level testing. The
100315 is a 300 Series redesign of the 100115 clock driver.
Features
n Low output to output skew (≤50 ps)
Logic Diagram
DS100319-1
Connection Diagram
Pin Names
CLKIN, CLKIN
CLK1–4, CLK1–4
TCLK
Description
Differential Clock Inputs
Differential Clock Outputs
Test Clock Input (Note 1)
Clock Input Select (Note 1)
Flatpak
CLKSEL
Note 1: TCLK and CLKSEL are single-ended inputs, with internal 50 kΩ pull-
down resistors.
DS100319-2
Truth Table
CLKSEL CLKIN
CLKIN TCLK CLKN
CLKN
L
L
L
H
X
X
H
L
X
X
L
L
H
L
H
L
H
H
X
X
H
L
H
H
=
=
=
L
H
X
Low Voltage Level
High Voltage Level
Don’t Care
© 1998 National Semiconductor Corporation
DS100319
www.national.com
NSC [ National Semiconductor ]
