August 1998
100331
Low Power Triple D Flip-Flop
General Description
Features
n 35% power reduction of the 100131
n 2000V ESD protection
The 100331 contains three D-type, edge-triggered master/
slave flip-flops with true and complement outputs, a Com-
mon Clock (CPC), and Master Set (MS) and Master Reset
(MR) inputs. Each flip-flop has individual Clock (CPn), Direct
Set (SDn) and Direct Clear (CDn) inputs. Data enters a mas-
ter when both CPn and CPC are LOW and transfers to a
slave when CPn or CPC (or both) go HIGH. The Master Set,
Master Reset and individual CDn and SDn inputs override
the Clock inputs. All inputs have 50 kΩ pull-down resistors.
n Pin/function compatible with 100131
=
n Voltage compensated operating range −4.2V to −5.7V
n Available to industrial grade temperature range
n Available to Standard Microcircuit Drawing (SMD)
5962-9153601
Logic Symbol
Pin Names
CP0–CP2
CPC
Description
Individual Clock Inputs
Common Clock Input
Data Inputs
D0–D2
CD0–CD2
SDn
Individual Direct Clear Inputs
Individual Direct Set Inputs
Master Reset Input
MR
MS
Master Set Input
Q0-Q2
Q0–Q2
Data Outputs
Complementary Data Outputs
DS100300-1
Connection Diagrams
24-Pin DIP
24-Pin Quad Cerpak
DS100300-3
DS100300-2
© 1998 National Semiconductor Corporation
DS100300
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