August 1998
100370
Low Power Universal Demultiplexer/Decoder
A1b with A2a unused (i.e., left open, tied to VEE or with LOW
signal applied). In the 1-of-8 mode, the Address inputs are
General Description
The 100370 universal demultiplexer/decoder functions as ei-
ther a dual 1-of-4 decoder or as a single 1-of-8 decoder, de-
pending on the signal applied to the Mode Control (M) input.
In the dual mode, each half has a pair of active-LOW Enable
(E) inputs. Pin assignments for the E inputs are such that in
the 1-of-8 mode they can easily be tied together in pairs to
provide two active-LOW enables (E1a to E1b, E2a to E2b).
Signals applied to auxiliary inputs Ha, Hb and Hc determine
whether the outputs are active HIGH or active LOW. In the
A
0a, A1a, A2a with A0b and A1b LOW or open. All inputs have
50 kΩ pulldown resistors.
Features
n 35% power reduction of the 100170
n 2000V ESD protection
n Pin/function compatible with 100170
=
n Voltage compensated operating range −4.2V to −5.7V
dual 1-of-4 mode the Address inputs are A0a, A1a and A0b
,
Logic Symbols
Single 1-of 8 Application
Dual 1-of-4 Application
DS100311-1
DS100311-4
Pin Names
Description
A
E
na, Anb
na, Enb
Address Inputs
Enable Inputs
M
Mode Control Input
Ha
Z0–Z3 (Z0a–Z3a
Polarity Select Input
Z4–Z7 (Z0b–Z3b
)
Hb
)
Polarity Select Input
Common Polarity
Select Input
Hc
Z0–Z7
Single 1-of-8
Data Outputs
Dual 1-of-4
Z
na, Znb
Data Outputs
© 1998 National Semiconductor Corporation
DS100311
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