June 1989
54174/DM54174/DM74174, 54175/DM54175/DM74175
Hex/Quad D Flip-Flops with Clear
General Description
Features
Y
Y
Y
Y
Y
174 contains six flip-flops with single-rail outputs
175 contains four flip-flops with double-rail outputs
Buffered clock and direct clear inputs
Individual data input to each flip-flop
Applications include:
These positive-edge triggered flip-flops utilize TTL circuitry
to implement D-type flip-flop logic. All have a direct clear
input, and the quad (175) version features complementary
outputs from each flip-flop.
Information at the D inputs meeting the setup and hold time
requirements is transferred to the Q outputs on the positive-
going edge of the clock pulse. Clock triggering occurs at a
particular voltage level and is not directly related to the tran-
sition time of the positive-going pulse. When the clock input
is at either the high or low level, the D input signal has no
effect at the output.
Buffer/storage registers
Shift registers
Pattern generators
Y
Y
Y
Typical clock frequency 40 MHz
Typical power dissipation per flip-flop 38 mW
Alternate Military/Aerospace device (54174, 54175) is
available. Contact a National Semiconductor Sales Of-
fice/Distributor for specifications.
Connection Diagrams
Dual-In-Line Package
Dual-In-Line Package
TL/F/6557–2
Order Number 54175DMQB, 54175FMQB, DM54175J,
DM54175W or DM74175N
TL/F/6557–1
Order Number 54174DMQB, 54174FMQB, DM54174J,
DM54174W or DM74174N
See NS Package Number J16A, N16E or W16A
See NS Package Number J16A, N16E or W16A
Function Table (Each Flip-Flop)
Inputs
Outputs
²
Q
Clear
Clock
D
Q
L
H
H
H
X
u
u
L
X
H
L
L
H
L
H
L
H
X
Q
Q
0
0
e
e
e
H
L
High Level (steady state)
Low Level (steady state)
Don’t Care
X
e
Transition from low to high level
u
0
e
Q
The level of Q before the indicated steady-state input conditions were established.
175 only
e
²
C
1995 National Semiconductor Corporation
TL/F/6557
RRD-B30M105/Printed in U. S. A.
NSC [ National Semiconductor ]
