July 1998
54ABT373
Octal Transparent Latch with TRI-STATE® Outputs
n Guaranteed multiple output switching specifications
n Output switching specified for both 50 pF and 250 pF
loads
n Guaranteed simultaneous switching, noise level and
dynamic threshold performance
n Guaranteed latchup protection
n High impedance glitch free bus loading during entire
power up and power down
General Description
The ’ABT373 consists of eight latches with TRI-STATE out-
puts for bus organized system applications. The flip-flops ap-
pear transparent to the data when Latch Enable (LE) is
HIGH. When LE is LOW, the data that meets the setup times
is latched. Data appears on the bus when the Output Enable
(OE) is LOW. When OE is HIGH the bus output is in the high
impedance state.
n Nondestructive hot insertion capability
n Standard Microcircuit Drawing (SMD) 5962-9321801
Features
n TRI-STATE outputs for bus interfacing
n Output sink capability of 48 mA, source capability of
24 mA
Ordering Code
Military
54ABT373J-QML
54ABT373W-QML
54ABT373E-QML
Package Number
J20A
Package Description
20-Lead Ceramic Dual-In-Line
W20A
20-Lead Cerpack
E20A
20-Lead Ceramic Leadless Chip Carrier, Type C
Connection Diagrams
Pin Assignment
for DIP and Flatpak
Pin Assignment
for LCC
DS100206-2
DS100206-1
Pin Names
Description
Data Inputs
D0–D7
LE
Latch Enable Input
(Active HIGH)
Output Enable Input
(Active LOW)
OE
O0–O7
TRI-STATE Latch
Outputs
TRI-STATE® is a registered trademark of National Semiconductor Corporation.
© 1998 National Semiconductor Corporation
DS100206
www.national.com
NSC [ National Semiconductor ]
