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54ABT373EQML 参数 Datasheet PDF下载

54ABT373EQML图片预览
型号: 54ABT373EQML
PDF下载: 下载PDF文件 查看货源
内容描述: [IC ABT SERIES, 8-BIT DRIVER, TRUE OUTPUT, CQCC20, CERAMIC, LCC-20, Bus Driver/Transceiver]
分类和应用: 锁存器
文件页数/大小: 16 页 / 331 K
品牌: NSC [ National Semiconductor ]
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September 1995  
54ABT/74ABT373  
Octal Transparent Latch with TRI-STATE Outputs  
É
Guaranteed output skew  
Y
General Description  
The ’ABT373 consists of eight latches with TRI-STATE out-  
Y
Guaranteed multiple output switching specifications  
Y
Output switching specified for both 50 pF and 250 pF  
puts for bus organized system applications. The flip-flops  
loads  
appear transparent to the data when Latch Enable (LE) is  
HIGH. When LE is LOW, the data that meets the setup  
times is latched. Data appears on the bus when the Output  
Enable (OE) is LOW. When OE is HIGH the bus output is in  
the high impedance state.  
Y
Guaranteed simultaneous switching, noise level and  
dynamic threshold performance  
Y
Guaranteed latchup protection  
Y
High impedance glitch free bus loading during entire  
power up and power down  
Y
Y
Nondestructive hot insertion capability  
Features  
Y
Standard Military Drawing (SMD) 5962-9321801  
TRI-STATE outputs for bus interfacing  
Y
Output sink capability of 64 mA, source capability of  
32 mA  
Package  
Commercial  
Military  
Package Description  
Number  
M20B  
M20D  
N20B  
74ABT373CSC (Note 1)  
74ABT373CSJ (Note 1)  
74ABT373CPC  
20-Lead (0.300 Wide) Molded Small Outline, JEDEC  
×
20-Lead (0.300 Wide) Molded Small Outline, EIAJ  
×
20-Lead (0.300 Wide) Molded Dual-In-Line  
×
54ABT373J/883  
J20A  
20-Lead Ceramic Dual-In-Line  
74ABT373CMSA (Note 1)  
MSA20 20-Lead Molded Shrink Small Outline, EIAJ Type II  
54ABT373W/883 W20A  
54ABT373E/883 E20A  
20-Lead Cerpack  
20-Lead Ceramic Leadless Chip Carrier, Type C  
74ABT373CMTC (Notes 1, 2)  
MTC20 20-Lead Molded Thin Shrink Small Outline, JEDEC  
e
Note 1: Devices also available in 13 reel. Use suffix  
×
Note 2: Contact factory for package availability.  
SCX, SJX, MSAX, and MTCX.  
Connection Diagrams  
Pin Assignment  
for DIP, SOIC, SSOP and Flatpak  
Pin Assignment  
for LCC  
Pin Names  
Description  
Data Inputs  
D D  
0
7
LE  
Latch Enable Input  
(Active HIGH)  
OE  
Output Enable Input  
(Active LOW)  
O O  
0
TRI-STATE Latch  
Outputs  
7
TL/F/11547–2  
TL/F/11547–1  
TRI-STATEÉ is a registered trademark of National Semiconductor Corporation.  
C
1995 National Semiconductor Corporation  
TL/F/11547  
RRD-B30M115/Printed in U. S. A.