August 1998
54AC175 • 54ACT175
Quad D Flip-Flop
n Buffered positive edge-triggered clock
n Asynchronous common reset
n True and complement output
n Outputs source/sink 24 mA
n ’ACT175 has TTL-compatible inputs
n Standard Microcircuit Drawing (SMD)
— ’AC175: 5962-89552
General Description
The ’AC/’ACT175 is a high-speed quad D flip-flop. The de-
vice is useful for general flip-flop requirements where clock
and clear inputs are common. The information on the D in-
puts is stored during the LOW-to-HIGH clock transition. Both
true and complemented outputs of each flip-flop are pro-
vided. A Master Reset input resets all flip-flops, independent
of the Clock or D inputs, when LOW.
— ’ACT175: 5962-89693
Features
n Edge-triggered D-type inputs
Logic Symbols
Connection Diagrams
Pin Assignment
for DIP and Flatpak
DS100278-1
IEEE/IEC
DS100278-3
Pin Assignment for LCC
DS100278-2
DS100278-4
Pin Names
D0–D3
CP
Description
Data Inputs
Clock Pulse Input
Master Reset Input
True Outputs
MR
Q0–Q3
Q0–Q3
Complement Outputs
FACT® is a registered trademark of Fairchild Semiconductor Corporation.
© 1998 National Semiconductor Corporation
DS100278
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