Connection Diagrams
Pin Assignment
for DIP SOIC and Flatpak
Pin Assignment
for LCC
TL F 9469– 1
TL F 9469 – 2
Unit Loading Fan Out
54F 74F
Pin Names
Description
UL
HIGH LOW
10 10
10 10
10 30
10 30
50 33 3
Input I
IH
I
IL
Output I
OH
I
OL
20
mA
b
0 6 mA
20
mA
b
0 6 mA
20
mA
b
1 8 mA
20
mA
b
1 8 mA
b
1 mA 20 mA
D
1
D
2
CP
1
CP
2
C
D1
C
D2
S
D1
S
D2
Q
1
Q
1
Q
2
Q
2
Data Inputs
Clock Pulse Inputs (Active Rising Edge)
Direct Clear Inputs (Active LOW)
Direct Set Inputs (Active LOW)
Outputs
Truth Table
Inputs
S
D
L
H
L
H
H
H
C
D
H
L
L
H
H
H
CP
X
X
X
L
L
L
D
X
X
X
h
l
X
Outputs
H (h)
e
HIGH Voltage Level
Q
H
L
H
H
L
Q
0
Q
L
H
H
L
H
Q
0
L (l)
e
LOW Voltage Level
X
e
Immaterial
Q
0
e
Previous Q (Q) before LOW-to-HIGH Clock Transition
Lower case letters indicate the state of the referenced input or output one
setup time prior to the LOW-to-HIGH clock transition
Logic Diagram
TL F 9469 – 5
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays
2
NSC [ NATIONAL SEMICONDUCTOR ]
