General Description
(Continued)
The eight latches of the DM54 74LS373 are transparent D-
type latches meaning that while the enable (G) is high the Q
outputs will follow the data (D) inputs When the enable is
taken low the output will be latched at the level of the data
that was set up
The eight flip-flops of the DM54 74LS374 are edge-trig-
gered D-type flip flops On the positive transition of the
clock the Q outputs will be set to the logic states that were
set up at the D inputs
A buffered output control input can be used to place the
eight outputs in either a normal logic state (high or low logic
levels) or a high-impedance state In the high-impedance
state the outputs neither load nor drive the bus lines signifi-
cantly
The output control does not affect the internal operation of
the latches or flip-flops That is the old data can be retained
or new data can be entered even while the outputs are off
Function Tables
DM54 74LS373
Output
Control
L
L
L
H
Enable
G
H
H
L
X
D
H
L
X
X
Output
H
L
Q
0
Z
Output
Control
L
L
L
H
DM54 74LS374
Clock
D
H
L
X
X
Output
H
L
Q
0
Z
u
u
L
X
H
e
High Level (Steady State) L
e
Low Level (Steady State) X
e
Don’t Care
e
Transition from low-to-high level Z
e
High Impedance State
Q
0
e
The level of the output before steady-state input conditions were established
u
Logic Diagrams
DM54 74LS373
Transparent Latches
DM54 74LS374
Positive-Edge-Triggered Flip-Flops
TL F 6431– 3
TL F 6431 – 4
2
NSC [ NATIONAL SEMICONDUCTOR ]
