ADC0801/ADC0802/ADC0803/ADC0804/ADC0805
AC Electrical Characteristics
Symbol
C
OUT
Parameter
TRI-STATE Output
Capacitance (Data Buffers)
(Continued)
The following specifications apply for V
CC
= 5 V
DC
and T
MIN
≤T
A
≤T
MAX
unless otherwise specified.
Conditions
Min
Typ
5
Max
7.5
Units
pF
CONTROL INPUTS
[Note: CLK IN (Pin 4) is the input of a Schmitt trigger circuit and is therefore specified separately]
V
IN
(1)
Logical “1” Input Voltage
V
CC
= 5.25 V
DC
2.0
15
(Except Pin 4 CLK IN)
V
IN
(0)
I
IN
(1)
I
IN
(0)
Logical “0” Input Voltage
(Except Pin 4 CLK IN)
Logical “1” Input Current
(All Inputs)
Logical “0” Input Current
(All Inputs)
CLOCK IN AND CLOCK R
V
T
+
V
T
−
V
H
V
OUT
(0)
V
OUT
(1)
CLK IN (Pin 4) Positive Going
Threshold Voltage
CLK IN (Pin 4) Negative
Going Threshold Voltage
CLK IN (Pin 4) Hysteresis
(V
T
+)−(V
T
−)
Logical “0” CLK R Output
Voltage
Logical “1” CLK R Output
Voltage
DATA OUTPUTS AND INTR
V
OUT
(0)
Logical “0” Output Voltage
Data Outputs
INTR Output
V
OUT
(1)
V
OUT
(1)
I
OUT
I
SOURCE
I
SINK
POWER SUPPLY
I
CC
Supply Current (Includes
Ladder Current)
ADC0801/02/03/04LCJ/05
ADC0804LCN/LCWM
f
CLK
= 640 kHz,
V
REF
/2 = NC, T
A
= 25˚C
and CS = 5V
1.1
1.9
1.8
2.5
Logical “1” Output Voltage
Logical “1” Output Voltage
TRI-STATE Disabled Output
Leakage (All Data Buffers)
I
OUT
= 1.6 mA, V
CC
= 4.75 V
DC
I
OUT
= 1.0 mA, V
CC
= 4.75 V
DC
I
O
= −360 µA, V
CC
= 4.75 V
DC
I
O
= −10 µA, V
CC
= 4.75 V
DC
V
OUT
= 0 V
DC
V
OUT
= 5 V
DC
V
OUT
Short to Gnd, T
A
= 25˚C
V
OUT
Short to V
CC
, T
A
= 25˚C
4.5
9.0
6
16
0.4
0.4
2.4
4.5
−3
3
I
O
= 360 µA
V
CC
= 4.75 V
DC
I
O
= −360 µA
V
CC
= 4.75 V
DC
2.4
0.4
0.6
1.3
2.0
1.5
1.8
2.1
2.7
3.1
3.5
V
IN
= 0 V
DC
−1
−0.005
V
IN
= 5 V
DC
0.005
1
V
CC
= 4.75 V
DC
0.8
V
DC
V
DC
µA
DC
µA
DC
V
DC
V
DC
V
DC
V
DC
V
DC
V
DC
V
DC
V
DC
V
DC
µA
DC
µA
DC
mA
DC
mA
DC
mA
mA
Note 1:
Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. DC and AC electrical specifications do not apply when operating
the device beyond its specified operating conditions.
Note 2:
All voltages are measured with respect to Gnd, unless otherwise specified. The separate A Gnd point should always be wired to the D Gnd.
Note 3:
A zener diode exists, internally, from V
CC
to Gnd and has a typical breakdown voltage of 7 V
DC
.
Note 4:
For V
IN
(−)≥ V
IN
(+) the digital output code will be 0000 0000. Two on-chip diodes are tied to each analog input (see block diagram) which will forward conduct
for analog input voltages one diode drop below ground or one diode drop greater than the V
CC
supply. Be careful, during testing at low V
CC
levels (4.5V), as high
level analog inputs (5V) can cause this input diode to conduct–especially at elevated temperatures, and cause errors for analog inputs near full-scale. The spec allows
50 mV forward bias of either diode. This means that as long as the analog V
IN
does not exceed the supply voltage by more than 50 mV, the output code will be correct.
To achieve an absolute 0 V
DC
to 5 V
DC
input voltage range will therefore require a minimum supply voltage of 4.950 V
DC
over temperature variations, initial tolerance
and loading.
Note 5:
Accuracy is guaranteed at f
CLK
= 640 kHz. At higher clock frequencies accuracy can degrade. For lower clock frequencies, the duty cycle limits can be ex-
tended so long as the minimum clock high time interval or minimum clock low time interval is no less than 275 ns.
Note 6:
With an asynchronous start pulse, up to 8 clock periods may be required before the internal clock phases are proper to start the conversion process. The
start request is internally latched, see
Figure 4
and section 2.0.
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