CLC016 Data Retiming PLL with Automatic Rate Selection
July 1998
CLC016
Data Retiming PLL with Automatic Rate Selection
General Description
National’s Comlinear CLC016 is a low-cost, monolithic, data
retiming phase-locked loop (PLL) designed for high-speed
serial clock and data recovery. The CLC016 simplifies high-
speed data recovery in multi-rate systems by incorporating
auto-rate select (ARS) circuitry on chip. This function allows
the user to configure the CLC016 to recognize up to four dif-
ferent data rates and automatically adjust to provide accu-
rate, low-jitter clock and data recovery. A single resistor is
used to set each data rate anywhere between 40 Mbps and
400 Mbps. No potentiometers, crystals, or other external ICs
are required to set the rate.
The CLC016 has output jitter of only 130 ps
pp
at a 270 Mbps
data rate and 0.25% fractional loop bandwidth. Low phase
detector output offset and low VCO injection combine to en-
sure that the CLC016 does not generate bit errors or large
phase transients in response to extreme fluctuations in data
transition density. The result is improved performance when
handling the pathological patterns inherent in the SMPTE
259M video industry standard.
The carrier detect and output mute functions may be used
together to automatically latch the outputs when no data is
present, preventing random transitions. The external loop fil-
ter allows the user to tailor the loop response to the specific
application needs. The CLC016 will operate with either +5V
or −5.2V power supplies. The serial data inputs and outputs,
as well as the recovered clock outputs, allow single- or
differential-ECL interfacing. The logic control inputs are TTL-
compatible.
Features
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Retimed data output
Recovered clock output
Auto and manual rate select modes
Four user-configurable data rates
No potentiometers required
External loop bandwidth control
Frequency detector for lock acquisition
Carrier detect output
Output MUTE function
Single supply operation: +5V or −5.2V
Low cost
Key Specifications
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Low jitter: 130 ps
pp
@
270 Mbps, 0.25% fractional loop
bandwidth (0.675 MHz)
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High data rates: 40 Mbps − 400 Mbps
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Low supply current: 100 mA, including output biasing
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Flexible fractional loop bandwidth: from 0.05% to 0.5%
Applications
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SMPTE 259M serial digital interfaces: NTSC/PAL, 4:2:2
component, 360 Mbps wide screen
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Serial digital video routing and distribution
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Clock and data recovery for high-speed data
transmission
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Re-synchronization of serial data for SONET/SDH, ATM,
CAD networks, medical and industrial imaging
DS100087-1
Order Number
CLC016ACQ
CLC016AJQ
Temperature
0˚C to +70˚C
–40˚C to +85˚C
Package
PLCC V28A
PLCC V28A
TRI-STATE
®
is a registered trademark of National Semiconductor Corporation.
© 1998 National Semiconductor Corporation
DS100087
www.national.com
NSC [ NATIONAL SEMICONDUCTOR ]
